Performance Evaluation of Load-Balanced Routing via Bounded Randomization

Future computer networks are expected to carry bursty traffic. Shortest-path routing protocols such as OSPF and RIP have t he disadvantage of causing bottlenecks due to their inherent single-path routing. That is, the uniformly selected shortest path between a source and a destination may become highly congested even when many other paths have low utilization. We propose a family of routing schemes that distribute data traffic over the whole network via bounded randomization; in this way, they remove bottlenecks and consequently improve network performance. For each data message to be sent from a source s to a destination d, each of the proposed routing protocols randomly choose an intermediate node e from a selected set of network nodes, and routes the data message along a shortest path from s to e. Then, it routes the data message via a shortest path from e to d. Intuitively, we would expect that this increase the effective bandwidth between each source-destination pair. Our simulation results indicate that the family of proposed load-balanced routing protocols distribute traffic evenly over the whole network and, in consequence, increases network performance with respect to throughput, message loss, message delay and link utilization. Moreover, implementing our scheme requires only a simple extension to any shortest-path routing protocol

Compact Oblivious Routing

Oblivious routing is an attractive paradigm for large distributed systems in which centralized control and frequent reconfigurations are infeasible or undesired (e.g., costly). Over the last almost 20 years, much progress has been made in devising oblivious routing schemes that guarantee close to optimal load and also algorithms for constructing such schemes efficiently have been designed. However, a common drawback of existing oblivious routing schemes is that they are not compact: they require large routing tables (of polynomial size), which does not scale. This paper presents the first oblivious routing scheme which guarantees close to optimal load and is compact at the same time - requiring routing tables of polylogarithmic size. Our algorithm maintains the polylogarithmic competitive ratio of existing algorithms, and is hence particularly well-suited for emerging large-scale networks

Constraint-Aware, Scalable, and Efficient Algorithms for Multi-Chip Power Module Layout Optimization

Moving towards an electrified world requires ultra high-density power converters. Electric vehicles, electrified aerospace, data centers, etc. are just a few fields among wide application areas of power electronic systems, where high-density power converters are essential. As a critical part of these power converters, power semiconductor modules and their layout optimization has been identified as a crucial step in achieving the maximum performance and density for wide bandgap technologies (i.e., GaN and SiC). New packaging technologies are also introduced to produce reliable and efficient multichip power module (MCPM) designs to push the current limits. The complexity of the emerging MCPM layouts is surpassing the capability of a manual, iterative design process to produce an optimum design with agile development requirements. An electronic design automation tool called PowerSynth has been introduced with ongoing research toward enhanced capabilities to speed up the optimized MCPM layout design process. This dissertation presents the PowerSynth progression timeline with the methodology updates and corresponding critical results compared to v1.1. The first released version (v1.1) of PowerSynth demonstrated the benefits of layout abstraction, and reduced-order modeling techniques to perform rapid optimization of the MCPM module compared to the traditional, manual, and iterative design approach. However, that version is limited by several key factors: layout representation technique, layout generation algorithms, iterative design-rule-checking (DRC), optimization algorithm candidates, etc. To address these limitations, and enhance PowerSynth’s capabilities, constraint-aware, scalable, and efficient algorithms have been developed and implemented. PowerSynth layout engine has evolved from v1.3 to v2.0 throughout the last five years to incorporate the algorithm updates and generate all 2D/2.5D/3D Manhattan layout solutions. These fundamental changes in the layout generation methodology have also called for updates in the performance modeling techniques and enabled exploring different optimization algorithms. The latest PowerSynth 2 architecture has been implemented to enable electro-thermo-mechanical and reliability optimization on 2D/2.5D/3D MCPM layouts, and set up a path toward cabinet-level optimization. PowerSynth v2.0 computer-aided design (CAD) flow has been hardware-validated through manufacturing and testing of an optimized novel 3D MCPM layout. The flow has shown significant speedup compared to the manual design flow with a comparable optimization result

Pragmatic Distribution Based Routing Cluster to Improve Energy Efficient Cluster lifetime for Wireless Sensor Networks

Energy consumed by the  sensor nodes are more sporadic in a sensor networks. A skilled way to bring down energy consumption and extend maximum life-time of any sensor present can be of evenly and unevenly distributed random area networks. Cluster heads are more responsible for the links between the source and destination. Energy consumption are much compare to member nodes of the network. Re-clustering will take place if the connectivity in the distributed network failure occurs in between the cluster networks  that will affects redundancy in the network efficiency. Hence, we propose  pragmatic distribution based routing cluster lifetime using fitness function (PDBRC) prototype  is better than the existing protocol using MATLAB 2021a simulation tool

Scheduling in Transactional Memory Systems: Models, Algorithms, and Evaluations

Transactional memory provides an alternative synchronization mechanism that removes many limitations of traditional lock-based synchronization so that concurrent program writing is easier than lock-based code in modern multicore architectures. The fundamental module in a transactional memory system is the transaction which represents a sequence of read and write operations that are performed atomically to a set of shared resources; transactions may conflict if they access the same shared resources. A transaction scheduling algorithm is used to handle these transaction conflicts and schedule appropriately the transactions. In this dissertation, we study transaction scheduling problem in several systems that differ through the variation of the intra-core communication cost in accessing shared resources. Symmetric communication costs imply tightly-coupled systems, asymmetric communication costs imply large-scale distributed systems, and partially asymmetric communication costs imply non-uniform memory access systems. We made several theoretical contributions providing tight, near-tight, and/or impossibility results on three different performance evaluation metrics: execution time, communication cost, and load, for any transaction scheduling algorithm. We then complement these theoretical results by experimental evaluations, whenever possible, showing their benefits in practical scenarios. To the best of our knowledge, the contributions of this dissertation are either the first of their kind or significant improvements over the best previously known results

NETWORK AND DOMAIN AUTOCONFIGURATION: A UNIFIED FRAMEWORK FOR LARGE MOBILE AD HOC NETWORKS

Configuration management is critical to correct and efficient operation of large networks. In those cases where the users and networks are dynamic and ad hoc, manual configuration quickly becomes too complex. The combination of the sheer number of nodes with the heterogeneity and dynamics makes it almost impossible for the system administrator to ensure good configuration or even ensure correct operation. To achieve the vision of pervasive computing, nodes must automatically discover their environment and self-configure, then must automatically reconfigure to adapt to changes. Protocols such as DHCP, DDNS and mDNS provide some degree of host autoconfiguration, but network administrators must still configure information such as address pools, routing protocols, or OSPF routing areas. Only limited progress has been made to automate the configuration of routers, servers and network topology. This dissertation proposes the autoconfiguration of most host, router and server information, including the automatic generation and maintenance of hierarchy, under the same architectural, algorithmic and protocol framework. The proposed unified framework consists of modules (DRCP, DCDP, YAP, ACA) responsible for the entity autoconfiguration and from a modified and well adjusted general optimization (Simulated Annealing) based algorithm for the domain autoconfiguration. Due to the generality of the optimization algorithm, the generated hierarchy can improve dynamically selected network performance aspects represented by appropriately designed objective functions and constraints. An indicative set related to the physical characteristics of the domains and node mobility is provided. Even though SA has been adjusted for faster convergence, it may still be unable to capture the dynamics of rapidly changing networks. Thus, a faster but suboptimal distributed hierarchy generation mechanism that follows the design philosophy of SA-based mechanism has also been introduced. Inevitably, due to network dynamics, the quality of the hierarchy will degrade. In such scenarios, the frequent reapplication of the expensive optimization based hierarchy generation is prohibitive. Hence, for extending the domain formation framework, distributed maintenance mechanisms have been proposed for reconstructing the feasibility and quality of the hierarchy by enforcing localized decisions. The proposed framework has been applied to provide solutions on some realistic network problems related to hierarchical routing and topology control

FatPaths: Routing in Supercomputers and Data Centers when Shortest Paths Fall Short

We introduce FatPaths: a simple, generic, and robust routing architecture that enables state-of-the-art low-diameter topologies such as Slim Fly to achieve unprecedented performance. FatPaths targets Ethernet stacks in both HPC supercomputers as well as cloud data centers and clusters. FatPaths exposes and exploits the rich ("fat") diversity of both minimal and non-minimal paths for high-performance multi-pathing. Moreover, FatPaths uses a redesigned "purified" transport layer that removes virtually all TCP performance issues (e.g., the slow start), and incorporates flowlet switching, a technique used to prevent packet reordering in TCP networks, to enable very simple and effective load balancing. Our design enables recent low-diameter topologies to outperform powerful Clos designs, achieving 15% higher net throughput at 2x lower latency for comparable cost. FatPaths will significantly accelerate Ethernet clusters that form more than 50% of the Top500 list and it may become a standard routing scheme for modern topologies

Smart Wireless Sensor Networks

The recent development of communication and sensor technology results in the growth of a new attractive and challenging area - wireless sensor networks (WSNs). A wireless sensor network which consists of a large number of sensor nodes is deployed in environmental fields to serve various applications. Facilitated with the ability of wireless communication and intelligent computation, these nodes become smart sensors which do not only perceive ambient physical parameters but also be able to process information, cooperate with each other and self-organize into the network. These new features assist the sensor nodes as well as the network to operate more efficiently in terms of both data acquisition and energy consumption. Special purposes of the applications require design and operation of WSNs different from conventional networks such as the internet. The network design must take into account of the objectives of specific applications. The nature of deployed environment must be considered. The limited of sensor nodes� resources such as memory, computational ability, communication bandwidth and energy source are the challenges in network design. A smart wireless sensor network must be able to deal with these constraints as well as to guarantee the connectivity, coverage, reliability and security of network's operation for a maximized lifetime. This book discusses various aspects of designing such smart wireless sensor networks. Main topics includes: design methodologies, network protocols and algorithms, quality of service management, coverage optimization, time synchronization and security techniques for sensor networks

Pragmatic Distribution Based Routing Cluster to Improve Energy Efficient Cluster lifetime for Wireless Sensor Networks

Energy consumed by the sensor nodes are more sporadic in a sensor networks. A skilled way to bring down energy consumption and extend maximum life-time of any sensor present can be of evenly and unevenly distributed random area networks. Cluster heads are more responsible for the links between the source and destination. Energy consumption are much compare to member nodes of the network. Re-clustering will take place if the connectivity in the distributed network failure occurs in between the cluster networks that will affects redundancy in the network efficiency. Hence, we propose pragmatic distribution based routing cluster lifetime using fitness function (PDBRC) prototype is better than the existing protocol using MATLAB 2021a simulation tool