Decoding: Codes and hardware implementation

The MST radars vary considerably from one installation to the next in the type of hardware, operating schedule and associated personnel. Most such systems do not have the computing power to decode in software when the decoding must be performed for each received pulse, as is required for certain sets of phase codes. These sets provide the best signal to sidelobe ratio when operating at the minimum band length allowed by the bandwidth of the transmitter. The development of the hardware phase decoder, and the applicability of each to decoding MST radar signals are discussed. A new design for a decoder which is very inexpensive to build, easy to add to an existing system and is capable of decoding on each received pulse using codes with a band length as short as one microsecond is presented

Hardware Implementation of the GPS authentication

In this paper, we explore new area/throughput trade- offs for the Girault, Poupard and Stern authentication protocol (GPS). This authentication protocol was selected in the NESSIE competition and is even part of the standard ISO/IEC 9798. The originality of our work comes from the fact that we exploit a fixed key to increase the throughput. It leads us to implement GPS using the Chapman constant multiplier. This parallel implementation is 40 times faster but 10 times bigger than the reference serial one. We propose to serialize this multiplier to reduce its area at the cost of lower throughput. Our hybrid Chapman's multiplier is 8 times faster but only twice bigger than the reference. Results presented here allow designers to adapt the performance of GPS authentication to their hardware resources. The complete GPS prover side is also integrated in the network stack of the PowWow sensor which contains an Actel IGLOO AGL250 FPGA as a proof of concept.Comment: ReConFig - International Conference on ReConFigurable Computing and FPGAs (2012

A VLSI implementation of the collision avoidance switch protocol for CAMB tree LANs

To solve a performance bottle neck in random access LANs due to packet collisions and their resolution, collision avoidance switches are introduced. These switches allow random access protocols to achieve high performance by resolving collisions among packets. A conventional hardware implementation of these switches is the use of TTL chips. In this implementation; a handful of TTL chips are required to forma single switch (e.g., 18 TTL chips are needed for an implementation of the CAMB switch [7]). Thus, implementation of a complete network, which requires several of these switches, could very well result in a large and complex hardware system.Today's modern chip technology allows us to pack large quantity of logic in a single chip. By transferring the conventional implementation of the collision avoidance switches into a VLSI chip, the complexity of the resultant hardware is greatly reduced, not to mention the improvement in hardware performance and ease of packaging.This report provides an overall study of the collision avoidance protocols for the tree LANs with emphasis on the implementation of collision avoidance switches. Hardware implementations of sorne of these switches are discussed. And a VLSI implementation of the CAMB switch protocol is introduced

A road towards the photonic hardware implementation of artificial cognitive circuits

Many technologies we use are inspired by nature. This happens in different domains, ranging from mechanics to optics to computer sciences. Nature has incredible potentialities that man still does not know or that he striving to learn through experience. These potentialities concern the ability to solve complex problems through approaches of various types of distributed intelligence. In fact, there are forms of intelligence in nature that differ from that of man, but are nevertheless exceedingly efficient. Man has often used as a model those forms of distributed intelligence that allow colonies of animals to develop places of housing or collective behaviors of extreme complexity. Recently, M. Alonzo et alii (Sci.Rep. 8, 5716 (2018)) published a hardware implementation to solve complex routing problems in modern information networks by exploiting the immense possibilities offered by light. This article presents an addressable photonic circuit based on the decision-making processes of ant colonies looking for food. When ants search for food, they modify their surroundings by leaving traces of pheromone, which may be reinforced and function as a type of path marker for when food has been found. This process is based on stigmergy, or the modification of the environment to implement distributed decision-making processes. The photonic hardware implementation that this work proposes is a photonic X-junction that simulates this stigmergic procedure. The experimental implementation is based on the use of non-linear substrates, i.e. materials that can be modified by light, simulating the modification induced by the ants on the surrounding environment when they leave the pheromone traces. Here, two laser beams generate two crossing channels in which the index of refraction is increased with respect to the whole substrate. These channels act as integrated waveguides (almost self-written optical fibers) within which optical information can be propagated (as happens for the ants that follow traces of pheromone already “written”). The proposed device is a X-junction with two crossing waveguides, whose refractive index contrast is defined by the intensities of the writing light beams. The higher the writing intensity, the greater the induced index variation, as if it were an increasingly intense pheromone trace. The information will follow the most contrasted harm of the junction, which is driven and eventually switched by the writing light intensity. Any optical information that will be sent to the device will follow the most intense trace, i.e. the most contrasted waveguide. The paper demonstrates a device that can be wholly operated using the light and that can be the basis of complex hardware configurations that might reproduce the stigmergic distributed intelligence. This is a highly significant innovation in the field of electronic and photonic technologies, within which artificial cognition and decision processes are implemented into a hardware circuit and not in a software code

A reconfigurable frame interpolation hardware architecture for high definition video

Since Frame Rate Up-Conversion (FRC) is started to be used in recent consumer electronics products like High Definition TV, real-time and low cost implementation of FRC algorithms has become very important. Therefore, in this paper, we propose a low cost hardware architecture for realtime implementation of frame interpolation algorithms. The proposed hardware architecture is reconfigurable and it allows adaptive selection of frame interpolation algorithms for each Macroblock. The proposed hardware architecture is implemented in VHDL and mapped to a low cost Xilinx XC3SD1800A-4 FPGA device. The implementation results show that the proposed hardware can run at 101 MHz on this FPGA and consumes 32 BRAMs and 15384 slices

Memristor Crossbar-based Hardware Implementation of IDS Method

Ink Drop Spread (IDS) is the engine of Active Learning Method (ALM), which is the methodology of soft computing. IDS, as a pattern-based processing unit, extracts useful information from a system subjected to modeling. In spite of its excellent potential in solving problems such as classification and modeling compared to other soft computing tools, finding its simple and fast hardware implementation is still a challenge. This paper describes a new hardware implementation of IDS method based on the memristor crossbar structure. In addition of simplicity, being completely real-time, having low latency and the ability to continue working after the occurrence of power breakdown are some of the advantages of our proposed circuit.Comment: 16 pages, 13 figures, Submitted to IEEE Transaction on Fuzzy System