17,234 research outputs found
Recommended from our members
Building safe software
Murphy is a set of techniques and tools under investigation for their potential in enhancing the safety of software. This paper describes some of the work which has been done and some which is planned
Optimized Compilation of Aggregated Instructions for Realistic Quantum Computers
Recent developments in engineering and algorithms have made real-world
applications in quantum computing possible in the near future. Existing quantum
programming languages and compilers use a quantum assembly language composed of
1- and 2-qubit (quantum bit) gates. Quantum compiler frameworks translate this
quantum assembly to electric signals (called control pulses) that implement the
specified computation on specific physical devices. However, there is a
mismatch between the operations defined by the 1- and 2-qubit logical ISA and
their underlying physical implementation, so the current practice of directly
translating logical instructions into control pulses results in inefficient,
high-latency programs. To address this inefficiency, we propose a universal
quantum compilation methodology that aggregates multiple logical operations
into larger units that manipulate up to 10 qubits at a time. Our methodology
then optimizes these aggregates by (1) finding commutative intermediate
operations that result in more efficient schedules and (2) creating custom
control pulses optimized for the aggregate (instead of individual 1- and
2-qubit operations). Compared to the standard gate-based compilation, the
proposed approach realizes a deeper vertical integration of high-level quantum
software and low-level, physical quantum hardware. We evaluate our approach on
important near-term quantum applications on simulations of superconducting
quantum architectures. Our proposed approach provides a mean speedup of
, with a maximum of . Because latency directly affects the
feasibility of quantum computation, our results not only improve performance
but also have the potential to enable quantum computation sooner than otherwise
possible.Comment: 13 pages, to apper in ASPLO
Towards the Model-Driven Engineering of Secure yet Safe Embedded Systems
We introduce SysML-Sec, a SysML-based Model-Driven Engineering environment
aimed at fostering the collaboration between system designers and security
experts at all methodological stages of the development of an embedded system.
A central issue in the design of an embedded system is the definition of the
hardware/software partitioning of the architecture of the system, which should
take place as early as possible. SysML-Sec aims to extend the relevance of this
analysis through the integration of security requirements and threats. In
particular, we propose an agile methodology whose aim is to assess early on the
impact of the security requirements and of the security mechanisms designed to
satisfy them over the safety of the system. Security concerns are captured in a
component-centric manner through existing SysML diagrams with only minimal
extensions. After the requirements captured are derived into security and
cryptographic mechanisms, security properties can be formally verified over
this design. To perform the latter, model transformation techniques are
implemented in the SysML-Sec toolchain in order to derive a ProVerif
specification from the SysML models. An automotive firmware flashing procedure
serves as a guiding example throughout our presentation.Comment: In Proceedings GraMSec 2014, arXiv:1404.163
EPICURE: A partitioning and co-design framework for reconfigurable computing
This paper presents a new design methodology able to bridge the gap between an abstract specification and a heterogeneous reconfigurable architecture. The EPICURE contribution is the result of a joint study on abstraction/refinement methods and a smart reconfigurable architecture within the formal Esterel design tools suite. The original points of this work are: (i) a generic HW/SW interface model, (ii) a specification methodology that handles the control, and includes efficient verification and HW/SW synthesis capabilities, (iii) a method for parallelism exploration based on abstract resources/performance estimation expressed in terms of area/delay tradeoffs, (iv) a HW/SW partitioning approach that refines the specification into explicit HW configurations and the associated SW control. The EPICURE framework shows how a cooperation of complementary methodologies and CAD tools associated with a relevant architecture can signficantly improve the designer productivity, especially in the context of reconfigurable architectures
A bibliography on formal methods for system specification, design and validation
Literature on the specification, design, verification, testing, and evaluation of avionics systems was surveyed, providing 655 citations. Journal papers, conference papers, and technical reports are included. Manual and computer-based methods were employed. Keywords used in the online search are listed
The hArtes Tool Chain
This chapter describes the different design steps needed to go from legacy code to a transformed application that can be efficiently mapped on the hArtes platform
A methodology to implement real-time applications on reconfigurable circuits
Special Issue Engineering of Configurable SystemsInternational audienceThis paper presents an extension of our AAA rapid prototyping methodology for the optimized implementation ofreal-time applications onto reconfigurable circuits. This extension is based on an unified model of factorized datadependence graphs as well to specify the application algorihtm, as to deduce the possible implementations ontoreconfigurable hardware, in terms of graphs transformations. This transformation flow has been implemented inSynDEx, a system level CAD software tool
- …