4,891 research outputs found

    Modern Diagnostics Techniques for Electrical Machines, Power Electronics, and Drives

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    © 2015 IEEE. Personal use of this material is permitted. Permissíon from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertisíng or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works.[EN] For the last ten years, at least three different special sections dealing with diagnostics in power electrical engineering have been published in the IEEE transactions on industrial electronics [1]-[5]. All of them had their specificities, but the last ones, starting in 2011, were more connected to relevant events organized on the topic. In fact, these events have been clearly the only international forums fully dedicated to diagnostics techniques in power electrical engineering. For this particular issue, it has been decided to separate the different submissions into six parts: state of the art; general methods; induction machines (IMs); synchronous machines (SMs); . electrical drives; power components and power converters. The second section includes only one state-of-the-art paper, which is dedicated to actual techniques implemented in both industry and research laboratories. The third section includes three papers on diagnostic techniques not specifically aimed at a particular type of machine. The fourth section includes three papers devoted to diagnostics of rotor faults, two dedicated to stator insulation issues, and four papers dealing with mechanical faults diagnosis in IMs. The fifth section includes papers focusing on different types of SMs. The first two papers deal with wound-rotor SMs, the following three papers are dedicated to permanent-magnet radial flux machines, and the last one deals with permanent-magnet axial flux machines. Regarding the types of faults analyzed, there are three papers devoted to the diagnosis of interturn short circuits in the stator windings, i.e., one dedicated to the detection and location of field-winding-to-ground faults and a paper devoted to the diagnosis of static eccentricities. In the sixth section, two papers investigate issues related to faults in drive sensors, and one is devoted to fault detections in the coupling inductors. The last section includes two papers devoted to diagnosis of faults and losses analysis in switching components of power converters.Capolino, G.; Antonino-Daviu, J.; Riera-Guasp, M. (2015). Modern Diagnostics Techniques for Electrical Machines, Power Electronics, and Drives. IEEE Transactions on Industrial Electronics. 62(3):1738-1745. doi:10.1109/TIE.2015.2391186S1738174562

    An Integrated Subharmonic Coupled-Oscillator Scheme for a 60-GHz Phased-Array Transmitter

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    This paper describes the design of an integrated coupled-oscillator array in SiGe for millimeter-wave applications. The design focuses on a scalable radio architecture where multiple dies are tiled to form larger arrays. A 2 × 2 oscillator array for a 60-GHz transmitter is fabricated with integrated power amplifiers and on-chip antennas. To lock between multiple dies, an injection-locking scheme appropriate for wire-bond interconnects is described. The 2 × 2 array demonstrates a 200–MHz locking range and 1 × 4 array formed by two adjacent chips has a 60-MHz locking range. The phase noise of the coupled oscillators is below 100 dBc/Hz at a 1-MHz offset when locked to an external reference. To the best of the authors’ knowledge, this is the highest frequency demonstration of coupled oscillators fabricated in a conventional silicon integrated-circuit process

    Chaos-based communication scheme using proportional and proportional-integral observers

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    In this paper, we propose a new chaos-based communication scheme using the observers. The novelty lies in the masking procedure that is employed to hide the confidential information using the chaotic oscillator. We use a combination of the addition and inclusion methods to mask the information. The performance of two observers, the proportional observer (P-observer) and the proportional integral observer (PI-observer) is compared that are employed as receivers for the proposed communication scheme. We show that the P-observer is not suitable scheme since it imposes unpractical constraints on the messages to be transmitted. On the other hand, we show that the PI-observer is the better solution because it allows greater flexibility in choosing the gains of the observer and does not impose any unpractical restrictions on the message

    Industrial applications of the Kalman filter:a review

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    ACE16K: The Third Generation of Mixed-Signal SIMD-CNN ACE Chips Toward VSoCs

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    Today, with 0.18-μm technologies mature and stable enough for mixed-signal design with a large variety of CMOS compatible optical sensors available and with 0.09-μm technologies knocking at the door of designers, we can face the design of integrated systems, instead of just integrated circuits. In fact, significant progress has been made in the last few years toward the realization of vision systems on chips (VSoCs). Such VSoCs are eventually targeted to integrate within a semiconductor substrate the functions of optical sensing, image processing in space and time, high-level processing, and the control of actuators. The consecutive generations of ACE chips define a roadmap toward flexible VSoCs. These chips consist of arrays of mixed-signal processing elements (PEs) which operate in accordance with single instruction multiple data (SIMD) computing architectures and exhibit the functional features of CNN Universal Machines. They have been conceived to cover the early stages of the visual processing path in a fully-parallel manner, and hence more efficiently than DSP-based systems. Across the different generations, different improvements and modifications have been made looking to converge with the newest discoveries of neurobiologists regarding the behavior of natural retinas. This paper presents considerations pertaining to the design of a member of the third generation of ACE chips, namely to the so-called ACE16k chip. This chip, designed in a 0.35-μm standard CMOS technology, contains about 3.75 million transistors and exhibits peak computing figures of 330 GOPS, 3.6 GOPS/mm2 and 82.5 GOPS/W. Each PE in the array contains a reconfigurable computing kernel capable of calculating linear convolutions on 3×3 neighborhoods in less than 1.5 μs, imagewise Boolean combinations in less than 200 ns, imagewise arithmetic operations in about 5 μs, and CNN-like temporal evolutions with a time constant of about 0.5 μs. Unfortunately, the many ideas underlying the design of this chip cannot be covered in a single paper; hence, this paper is focused on, first, placing the ACE16k in the ACE chip roadmap and, then, discussing the most significant modifications of ACE16K versus its predecessors in the family.LOCUST IST2001—38 097VISTA TIC2003—09 817 - C02—01Office of Naval Research N000 140 210 88

    A Bio-Inspired Two-Layer Mixed-Signal Flexible Programmable Chip for Early Vision

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    A bio-inspired model for an analog programmable array processor (APAP), based on studies on the vertebrate retina, has permitted the realization of complex programmable spatio-temporal dynamics in VLSI. This model mimics the way in which images are processed in the visual pathway, what renders a feasible alternative for the implementation of early vision tasks in standard technologies. A prototype chip has been designed and fabricated in 0.5 μm CMOS. It renders a computing power per silicon area and power consumption that is amongst the highest reported for a single chip. The details of the bio-inspired network model, the analog building block design challenges and trade-offs and some functional tests results are presented in this paper.Office of Naval Research (USA) N-000140210884European Commission IST-1999-19007Ministerio de Ciencia y Tecnología TIC1999-082

    FPGAs in Industrial Control Applications

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    The aim of this paper is to review the state-of-the-art of Field Programmable Gate Array (FPGA) technologies and their contribution to industrial control applications. Authors start by addressing various research fields which can exploit the advantages of FPGAs. The features of these devices are then presented, followed by their corresponding design tools. To illustrate the benefits of using FPGAs in the case of complex control applications, a sensorless motor controller has been treated. This controller is based on the Extended Kalman Filter. Its development has been made according to a dedicated design methodology, which is also discussed. The use of FPGAs to implement artificial intelligence-based industrial controllers is then briefly reviewed. The final section presents two short case studies of Neural Network control systems designs targeting FPGAs

    A study of FPGA-based System-on-Chip designs for real-time industrial application

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    This paper shows the benefits of the Field Programming Gate Array (FPGAs) in industrial control applications. The author starts by addressing the benefits of FPGA and where it is useful. As well as, the author has done some FPGA’s evaluation researches on the FPGA performing explaining the performance of the FPGA and the design tools. To show the benefits of the FPGA, an industrial application example has been used. The application is a real-time face detection and tracking using FPGA. Face tracking will depend on calculating the centroid of each detected region. A DE2-SoC Altera board has been used to implement this application. The application based on few algorithms that filter the captured images to detect them. These algorithms have been translated to a Verilog code to run it on the DE2-SoC boar
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