Low-Dimensional Materials for Disruptive Microwave Antennas Design

This chapter is devoted to a complete analysis of remarkable electromagnetic properties of nanomaterials suitable for antenna design miniaturization. After a review of state of the art mesoscopic scale modeling tools and characterization techniques in microwave domain, new approaches based on wideband material parameters identification (complex permittivity and conductivity) will be described from impedance equivalence formulation achievement by de-embedding techniques applicable in integrated technology or in free space. A focus on performances of 1D materials such as vertically aligned multi-wall carbon nanotube (VA-MWCNT) bundles, from theory to technology, will be presented as a disruptive demonstration for defense and civil applications as in radar systems

Solid State Circuits Technologies

The evolution of solid-state circuit technology has a long history within a relatively short period of time. This technology has lead to the modern information society that connects us and tools, a large market, and many types of products and applications. The solid-state circuit technology continuously evolves via breakthroughs and improvements every year. This book is devoted to review and present novel approaches for some of the main issues involved in this exciting and vigorous technology. The book is composed of 22 chapters, written by authors coming from 30 different institutions located in 12 different countries throughout the Americas, Asia and Europe. Thus, reflecting the wide international contribution to the book. The broad range of subjects presented in the book offers a general overview of the main issues in modern solid-state circuit technology. Furthermore, the book offers an in depth analysis on specific subjects for specialists. We believe the book is of great scientific and educational value for many readers. I am profoundly indebted to the support provided by all of those involved in the work. First and foremost I would like to acknowledge and thank the authors who worked hard and generously agreed to share their results and knowledge. Second I would like to express my gratitude to the Intech team that invited me to edit the book and give me their full support and a fruitful experience while working together to combine this book

Through Silicon Via Field-Effect Transistor with Hafnia-based Ferroelectrics and the Doping of Silicon by Gallium Implantation Utilizing a Focused Ion Beam System

3-dimensional integration has become a standard to further increase the transistor density and to enhance the integrated functionality in microchips. Integrated circuits are stacked on top of each other and copper-filled through-silicon VIAs (TSVs) are the industry-accepted choice for their vertical electrical connection. The aim of this work is to functionalize the TSVs by implementing vertical field-effect transistors inside the via holes. The front and back sides of 200 ... 300 µm thin silicon wafers were doped to create the source/drain regions of n- and p-FETs. The TSVFETs showed very stable saturation currents and on/off current ratios of about 10^6 (n-TSVFET) and 10^3 (p-TSVFET) for a gate voltage magnitude of 4V. The use of hafnium zirconium oxide on a thin SiO_2 interface layer as gate dielectric material in a p-TSVFET, enabled the implementation of a charge trapping memory inside the TSVs, showing a memory window of about 1V. This allows the non-volatile storage of the transistor on/off state. In addition, the demonstration of the use of gallium as the source/drain dopant in planar p-FET test structures (ion implanted from a focused ion beam tool) paves the way for maskless doping and for a process flow with a low thermal budget. It was shown, that ion implanted gallium can be activated and annealed at relatively low temperatures of 500 °C ... 700 °C.:Abstract / Kurzzusammenfassung Danksagung Index I List of Figures III List of Tables X List of Symbols XI List of Abbreviations XV 1 Introduction 1 2 Fundamentals 5 2.1 Metal Oxide Semiconductor Field Effect Transistors (MOSFETs) 5 2.1.1 Historical Development - Technological Advancements 7 2.1.2 Field-Effect Transistors in Semiconductor Memories 10 2.2 3D Integration and the Use of TSVs (Through Silicon VIAs) 16 2.3 Doping of Silicon 19 2.3.1 Doping by Thermal Diffusion 20 2.3.2 Doping by Ion Implantation 22 3 Electrical Characterization 24 3.1 Resistivity Measurements 24 3.1.1 Resistance Determination by Four-Point Probes Measurement 24 3.1.2 Contact Resistivity 27 3.1.3 Doping Concentration 32 3.2 C-V Measurements 35 3.2.1 Fundamentals of MIS C-V Measurements 35 3.2.2 Interpretation of C-V Measurements 37 3.3 Transistor Measurements 41 3.3.1 Output Characteristics (I_D-V_D) 41 3.3.2 Transfer Characteristics (I_D-V_G) 42 4 TSV Transistor 45 4.1 Idea and Motivation 45 4.2 Design and Layout of the TSV Transistor 47 4.2.1 Design of the TSV Transistor Structures 47 4.2.2 Test Structures for Planar FETs 48 5 Variations in the Integration Scheme of the TSV Transistor 51 5.1 Doping by Diffusion from Thin Films 51 5.1.1 Determination of Doping Profiles 52 5.1.2 n- and p- TSVFETs Doped Manufactures by the Use of the Diffusion Technique 59 5.2 Ferroelectric Hafnium-Zirconium-Oxide (HZO) in the Gate Stack 81 5.2.1 Planar ferroelectric p-MOSFETs Doped by Thermal Diffusion 82 5.2.2 p-TSVFETs with Hafnium-Zirconium-Oxide Metal Gate 90 5.3 Doping by Ion Implantation of Gallium with a Focused Ion Beam (FIB) Tool 96 5.3.1 Ga doped Si Diodes 97 5.3.2 Planar p-MOSFETs Doped by Ga Implantation 108 5.3.3 Proposal for a parallel integration of Cu TSVs and p-TSVFETs 117 6 Summary and Outlook 120 Bibliography XVIII A Appendix XXXVI A.1 Resistivity and Dopant Density XXXVI A.2 Mask set for the TSVFET XXXVII A.3 Mask Design of the Planar Test Structures XXXVIII Curriculum Vitae XXXIX List of Scientific Publications XL

Self-Aligned 3D Chip Integration Technology and Through-Silicon Serial Data Transmission

The emerging three-dimensional (3D) integration technology is expected to lead to an industry paradigm shift due to its tremendous benefits. Intense research activities are going on about technology, simulation, design, and product prototypes. This thesis work aims at fabricating through-silicon vias (TSVs) on diced processor chips, and later bonding them into a 3D-stacked chip. How to handle and process delicate processor chips with high alignment precision is a key issue. The TSV process to be developed also needs to adapt to this constraint. Four TSV processes have been studied. Among them, the ring-trench TSV process demonstrates the feasibility of fabricating TSVs with the prevailing dimensions, and the whole-through TSV process achieves the first dummy chip post-processed with TSVs in EPFL although the dimension is rather large to keep a reasonable aspect ratio (AR). Four self-alignment (SA) techniques have been investigated, among which the gravitational SA and the hydrophobic SA are found to be quite promising. Using gravitational SA, we come to the conclusion that cavities in silicon carrier wafer with a profile angle of 60° can align the chips with less than 20 µm inaccuracies. The alignment precision can be improved after adopting more advanced dicing tools instead of using the traditional dicing saws and larger cavity profile angle. Such inaccuracy will be sufficient to align the relatively large TSVs for general products such as 3D image sensors. By fabricating bottom TSVs in the carrier wafer, a 3D silicon interposer idea has been proposed to stack another chip, e.g. a processor chip, on the other side of the carrier wafer. But stacking microprocessor chips fabricated with TSVs will require higher alignment precision. A hydrophobic SA technique using the surface tension force generated by the water-to-air interfaces around the pads can greatly reduce the alignment inaccuracy to less than 1 µm. This low-cost and high throughput SA procedure is processed in air, fully-compatible with current fabrication technologies, and highly stable and repeatable. We present a theoretical meniscus model to predict SA results and to provide the design rules. This technique is quite promising for advanced 3D applications involving logic and heterogeneous stacking. As TSVs' dimensions in the chip-level 3D integration are constrained by the chip-level processes, such as bonding, the smallest TSVs might still be about 5 µm. Thus, the area occupied by the TSVs cannot be neglected. Fortunately, TSVs can withstand very high bandwidths, meaning that data can be serialized and transmitted using less numbers of TSVs. With 20 µm TSVs, the 2-Gb/s 8:1 serial link implemented saves 75% of the area of its 8-bit parallel counterpart. The quasi-serial link proposed can effectively balance the inter-layer bandwidth and the serial links' area consumption. The area model of the serial or quasi-serial links working under higher frequencies provides some guidelines to choose the proper serial link design, and it also predicts that when TSV diameter shrinks to 5 µm, it will be difficult to keep this area benefit if without some novel circuit design techniques. As the serial links can be implemented with less area, the bandwidth per unit area is increased. Two scenarios are studied, single-port memory access and multi-port memory access. The expanded inter-layer bandwidth by serialization does not improve the system performance because of the bus-bottleneck problem. In the latter scenario, the inter-layer ultra-wide bandwidth can be exploited as each memory bank can be accessed randomly through the NoC. Thus further widening the inter-layer bandwidth through serialization, the system performance will be improved

LSI配線用ナノ炭素材料の合成プロセスに関する研究

Tohoku University高桑雄二課

Optimisation du procédé de réalisation pour l'intégration séquentielle 3D des transistors CMOS FDSOI

L activation à basse température est prometteuse pour l intégration 3D séquentielle où lebudget thermique du transistor supérieur est limité (<650 C) pour ne pas dégrader letransistor inférieur, mais aussi dans le cas d une intégration planaire afin d atteindre des EOTultra fines et de contrôler le travail de sortie de la grille sans recourir à une intégration de type gate-last . Dans ce travail, l activation par recroissance en phase solide (SPER) a étéétudiée afin de réduire le budget thermique de l activation des dopants.L activation à basse température présente plusieurs inconvénients. Les travauxprécédents montrent que les fuites de jonctions sont plus importantes dans ces dispositifs.Ensuite, des fortes désactivations de dopants ont été observées. Troisièmement, la faiblediffusion des dopants rend difficile la connexion des jonctions source et drain avec le canal.Dans ce travail, il est montré que dans un transistor FDSOI, l augmentation des fuites dejonctions et la désactivation du Bore peuvent être évités grâce à la présence de l oxyde enterré.De plus les conditions d implantation ont été optimisées et les transistors activés à650 C atteignent les performances des transistors de référence.Low temperature (LT) process is gaining interest in the frame of 3D sequentialintegration where limited thermal budget (<650 C) is needed for top FET to preserve bottomFET from any degradation and also in the standard planar integration for achieving ultra-thinEOT and work function control with high-k metal gate without gate-last integration scheme.In this work, LT Solid Phase Epitaxial Regrowth (SPER) has been investigated for reducingthe most critical thermal budget which is dopant activation.From previous works, LT activated devices face several challenges: First, higher junctionleakage limits their application to high performance devices. Secondly, strong deactivation ofthe metastable activated dopants was observed with post anneals. Thirdly, the dopant weakdiffusion makes it difficult to connect the channel with S/D.In this work, it is shown that the use of FDSOI enables to overcome junction leakage andBoron deactivation issues thanks to the defect cutting off and sinking effect of buried oxide.As a consequence, dopant deactivation in FDSOI devices is no longer an issue. Finally,implants conditions of LT transistors have been optimized to reach similar performance thanits standard high temperature counterparts.SAVOIE-SCD - Bib.électronique (730659901) / SudocGRENOBLE1/INP-Bib.électronique (384210012) / SudocGRENOBLE2/3-Bib.électronique (384219901) / SudocSudocFranceF

Integrated Circuits/Microchips

With the world marching inexorably towards the fourth industrial revolution (IR 4.0), one is now embracing lives with artificial intelligence (AI), the Internet of Things (IoTs), virtual reality (VR) and 5G technology. Wherever we are, whatever we are doing, there are electronic devices that we rely indispensably on. While some of these technologies, such as those fueled with smart, autonomous systems, are seemingly precocious; others have existed for quite a while. These devices range from simple home appliances, entertainment media to complex aeronautical instruments. Clearly, the daily lives of mankind today are interwoven seamlessly with electronics. Surprising as it may seem, the cornerstone that empowers these electronic devices is nothing more than a mere diminutive semiconductor cube block. More colloquially referred to as the Very-Large-Scale-Integration (VLSI) chip or an integrated circuit (IC) chip or simply a microchip, this semiconductor cube block, approximately the size of a grain of rice, is composed of millions to billions of transistors. The transistors are interconnected in such a way that allows electrical circuitries for certain applications to be realized. Some of these chips serve specific permanent applications and are known as Application Specific Integrated Circuits (ASICS); while, others are computing processors which could be programmed for diverse applications. The computer processor, together with its supporting hardware and user interfaces, is known as an embedded system.In this book, a variety of topics related to microchips are extensively illustrated. The topics encompass the physics of the microchip device, as well as its design methods and applications

Towards Faster Data Transfer by Spoof Plasmonics

With the emergence of complex architectures in modern electronics such as multi-chip modules, the increasing electromagnetic cross-talk in the circuitry causes a serious issue for high-speed, reliable data transfer among the chips. This thesis aims at developing a cross-talk resilient communication technology by utilizing a special form of electromagnetic mode, called spoof surface plasmon polariton for information transfer. The technique is based on the fact that a metal wire with periodic sub-wavelength patterns can support the propagation of confined electromagnetic mode, which can suppress cross-talk noise among the adjacent channels; and thus outperform conventional electrical interconnects in a parallel, high channel density data-bus. My developed model shows that, with 1 THz carrier frequency, the optimal design of cross-talk resilient spoof plasmon data-bus would allow each channel to support as high as 300 Gbps data, the bandwidth density can reach 1 Tbps per millimeter width of data-bus, and the digital pulse modulated carrier can travel more than 5 mm distance on the substrate. I have demonstrated that spoof plasmonic interconnects, comprised of patterned metallic conductors, can simultaneously accommodate electronic TEM mode, which is superior in cross-talk suppression at low-frequencies; and spoof plasmon mode, which is superior at high-frequencies. The research work is divided into two complementary parts: developing a theory for electromagnetic property analysis of spoof plasmon waveguide, and manipulating these properties for high-speed data transfer. Based on the theory developed, I investigated the complex interplay among various figure-of-merits of data transfer in spoof plasmonics, such as bandwidth density, propagation loss, thermal noise, speed of modulation, etc. My developed model predicts that with the availability of 1 THz carrier, the bit-error-rate of spoof plasmon data bus, subject to thermal noise would be $sim10^{-8}$ while the Shannon information capacity of the bus would be $10$ Tbps/mm. The model also predicts that, by proper designing of the modulator, it can be possible to alter the transmission property of the waveguide over one-fifth ($1/5$) of the spoof plasmon band which spans from DC frequency to the frequency of spoof plasmon resonance. To exemplify, if the spoof plasmon resonance is set at $1$ THz, then we can achieve more than $200$ Gbps speed of modulation with a very high extinction ratio, assuming the switching latency of the transistors at our disposal is negligible to the time-resolution of interest. We envision spoof plasmonic interconnects to constitute the next generation communication technology that will be transferring data at hundreds of Gigabit per second (Gbps) speed among different chips on a multi-chip module (MCM) carrier or system-on-chip (SoC) packaging.PHDElectrical EngineeringUniversity of Michigan, Horace H. Rackham School of Graduate Studieshttp://deepblue.lib.umich.edu/bitstream/2027.42/163041/1/srjoy_1.pd