Algorithmic techniques for physical design : macro placement and under-the-cell routing

With the increase of chip component density and new manufacturability constraints imposed by modern technology nodes, the role of algorithms for electronic design automation is key to the successful implementation of integrated circuits. Two of the critical steps in the physical design flows are macro placement and ensuring all design rules are honored after timing closure. This thesis proposes contributions to help in these stages, easing time-consuming manual steps and helping physical design engineers to obtain better layouts in reduced turnaround time. The first contribution is under-the-cell routing, a proposal to systematically connect standard cell components via lateral pins in the lower metal layers. The aim is to reduce congestion in the upper metal layers caused by extra metal and vias, decreasing the number of design rule violations. To allow cells to connect by abutment, a standard cell library is enriched with instances containing lateral pins in a pre-selected sharing track. Algorithms are proposed to maximize the numbers of connections via lateral connection by mapping placed cell instances to layouts with lateral pins, and proposing local placement modifications to increase the opportunities for such connections. Experimental results show a significant decrease in the number of pins, vias, and in number of design rule violations, with negligible impact on wirelength and timing. The second contribution, done in collaboration with eSilicon (a leading ASIC design company), is the creation of HiDaP, a macro placement tool for modern industrial designs. The proposed approach follows a multilevel scheme to floorplan hierarchical blocks, composed of macros and standard cells. By exploiting RTL information available in the netlist, the dataflow affinity between these blocks is modeled and minimized to find a macro placement with good wirelength and timing properties. The approach is further extended to allow additional engineer input, such as preferred macro locations, and also spectral and force methods to guide the floorplanning search. Experimental results show that the layouts generated by HiDaP outperforms those obtained by a state-of-the-art EDA physical design software, with similar wirelength and better timing when compared to manually designed tape-out ready macro placements. Layouts obtained by HiDaP have successfully been brought to near timing closure with one to two rounds of small modifications by physical design engineers. HiDaP has been fully integrated in the design flows of the company and its development remains an ongoing effort.A causa de l'increment de la densitat de components en els xip i les noves restriccions de disseny imposades pels últims nodes de fabricació, el rol de l'algorísmia en l'automatització del disseny electrònic ha esdevingut clau per poder implementar circuits integrats. Dos dels passos crucials en el procés de disseny físic és el placement de macros i assegurar la correcció de les regles de disseny un cop les restriccions de timing del circuit són satisfetes. Aquesta tesi proposa contribucions per ajudar en aquests dos reptes, facilitant laboriosos passos manuals en el procés i ajudant als enginyers de disseny físic a obtenir millors resultats en menys temps. La primera contribució és el routing "under-the-cell", una proposta per connectar cel·les estàndard usant pins laterals en les capes de metall inferior de manera sistemàtica. L'objectiu és reduir la congestió en les capes de metall superior causades per l'ús de metall i vies, i així disminuir el nombre de violacions de regles de disseny. Per permetre la connexió lateral de cel·les, estenem una llibreria de cel·les estàndard amb dissenys que incorporen connexions laterals. També proposem modificacions locals al placement per permetre explotar aquest tipus de connexions més sovint. Els resultats experimentals mostren una reducció significativa en el nombre de pins, vies i nombre de violacions de regles de disseny, amb un impacte negligible en wirelength i timing. La segona contribució, desenvolupada en col·laboració amb eSilicon (una empresa capdavantera en disseny ASIC), és el desenvolupament de HiDaP, una eina de macro placement per a dissenys industrials actuals. La proposta segueix un procés multinivell per fer el floorplan de blocks jeràrquics, formats per macros i cel·les estàndard. Mitjançant la informació RTL disponible en la netlist, l'afinitat de dataflow entre els mòduls es modela i minimitza per trobar macro placements amb bones propietats de wirelength i timing. La proposta també incorpora la possibilitat de rebre input addicional de l'enginyer, com ara suggeriments de les posicions de les macros. Finalment, també usa mètodes espectrals i de forçes per guiar la cerca de floorplans. Els resultats experimentals mostren que els dissenys generats amb HiDaP són millors que els obtinguts per eines comercials capdavanteres de EDA. Els resultats també mostren que els dissenys presentats poden obtenir un wirelength similar i millor timing que macro placements obtinguts manualment, usats per fabricació. Alguns dissenys obtinguts per HiDaP s'han dut fins a timing-closure en una o dues rondes de modificacions incrementals per part d'enginyers de disseny físic. L'eina s'ha integrat en el procés de disseny de eSilicon i el seu desenvolupament continua més enllà de les aportacions a aquesta tesi.Postprint (published version

Algorithmic techniques for physical design : macro placement and under-the-cell routing

With the increase of chip component density and new manufacturability constraints imposed by modern technology nodes, the role of algorithms for electronic design automation is key to the successful implementation of integrated circuits. Two of the critical steps in the physical design flows are macro placement and ensuring all design rules are honored after timing closure. This thesis proposes contributions to help in these stages, easing time-consuming manual steps and helping physical design engineers to obtain better layouts in reduced turnaround time. The first contribution is under-the-cell routing, a proposal to systematically connect standard cell components via lateral pins in the lower metal layers. The aim is to reduce congestion in the upper metal layers caused by extra metal and vias, decreasing the number of design rule violations. To allow cells to connect by abutment, a standard cell library is enriched with instances containing lateral pins in a pre-selected sharing track. Algorithms are proposed to maximize the numbers of connections via lateral connection by mapping placed cell instances to layouts with lateral pins, and proposing local placement modifications to increase the opportunities for such connections. Experimental results show a significant decrease in the number of pins, vias, and in number of design rule violations, with negligible impact on wirelength and timing. The second contribution, done in collaboration with eSilicon (a leading ASIC design company), is the creation of HiDaP, a macro placement tool for modern industrial designs. The proposed approach follows a multilevel scheme to floorplan hierarchical blocks, composed of macros and standard cells. By exploiting RTL information available in the netlist, the dataflow affinity between these blocks is modeled and minimized to find a macro placement with good wirelength and timing properties. The approach is further extended to allow additional engineer input, such as preferred macro locations, and also spectral and force methods to guide the floorplanning search. Experimental results show that the layouts generated by HiDaP outperforms those obtained by a state-of-the-art EDA physical design software, with similar wirelength and better timing when compared to manually designed tape-out ready macro placements. Layouts obtained by HiDaP have successfully been brought to near timing closure with one to two rounds of small modifications by physical design engineers. HiDaP has been fully integrated in the design flows of the company and its development remains an ongoing effort.A causa de l'increment de la densitat de components en els xip i les noves restriccions de disseny imposades pels últims nodes de fabricació, el rol de l'algorísmia en l'automatització del disseny electrònic ha esdevingut clau per poder implementar circuits integrats. Dos dels passos crucials en el procés de disseny físic és el placement de macros i assegurar la correcció de les regles de disseny un cop les restriccions de timing del circuit són satisfetes. Aquesta tesi proposa contribucions per ajudar en aquests dos reptes, facilitant laboriosos passos manuals en el procés i ajudant als enginyers de disseny físic a obtenir millors resultats en menys temps. La primera contribució és el routing "under-the-cell", una proposta per connectar cel·les estàndard usant pins laterals en les capes de metall inferior de manera sistemàtica. L'objectiu és reduir la congestió en les capes de metall superior causades per l'ús de metall i vies, i així disminuir el nombre de violacions de regles de disseny. Per permetre la connexió lateral de cel·les, estenem una llibreria de cel·les estàndard amb dissenys que incorporen connexions laterals. També proposem modificacions locals al placement per permetre explotar aquest tipus de connexions més sovint. Els resultats experimentals mostren una reducció significativa en el nombre de pins, vies i nombre de violacions de regles de disseny, amb un impacte negligible en wirelength i timing. La segona contribució, desenvolupada en col·laboració amb eSilicon (una empresa capdavantera en disseny ASIC), és el desenvolupament de HiDaP, una eina de macro placement per a dissenys industrials actuals. La proposta segueix un procés multinivell per fer el floorplan de blocks jeràrquics, formats per macros i cel·les estàndard. Mitjançant la informació RTL disponible en la netlist, l'afinitat de dataflow entre els mòduls es modela i minimitza per trobar macro placements amb bones propietats de wirelength i timing. La proposta també incorpora la possibilitat de rebre input addicional de l'enginyer, com ara suggeriments de les posicions de les macros. Finalment, també usa mètodes espectrals i de forçes per guiar la cerca de floorplans. Els resultats experimentals mostren que els dissenys generats amb HiDaP són millors que els obtinguts per eines comercials capdavanteres de EDA. Els resultats també mostren que els dissenys presentats poden obtenir un wirelength similar i millor timing que macro placements obtinguts manualment, usats per fabricació. Alguns dissenys obtinguts per HiDaP s'han dut fins a timing-closure en una o dues rondes de modificacions incrementals per part d'enginyers de disseny físic. L'eina s'ha integrat en el procés de disseny de eSilicon i el seu desenvolupament continua més enllà de les aportacions a aquesta tesi

The Flip Diameter of Rectangulations and Convex Subdivisions

We study the configuration space of rectangulations and convex subdivisions of $n$ points in the plane. It is shown that a sequence of $O(n\log n)$ elementary flip and rotate operations can transform any rectangulation to any other rectangulation on the same set of $n$ points. This bound is the best possible for some point sets, while $\Theta(n)$ operations are sufficient and necessary for others. Some of our bounds generalize to convex subdivisions of $n$ points in the plane.Comment: 17 pages, 12 figures, an extended abstract has been presented at LATIN 201

스캔 도면을 활용한 이동약자용 실내 그래프 데이터베이스 구축

학위논문(박사) -- 서울대학교대학원 : 공과대학 건설환경공학부, 2021.8. 박슬아.사람들의 실내 활동이 다양해지면서 건물의 규모가 커지고 구조가 복잡해지고 있다. 이러한 실내 환경의 변화는 교통약자의 이동성 보장에 대한 사회적 관심을 증가시켰으며, 교통약자 맞춤형 실내 라우팅 서비스에 대한 수요 또한 증가시켰다. 특히 많은 이동 제약을 가지는 이동약자 대상 서비스의 경우에는, 최적 경로를 계획하는 과정에서 개인의 선호나 경험이 반영된 개인화된 서비스로 범위가 확장되고 있다. 이러한 배경에서, 스키마가 유연하고 데이터의 가공 및 처리가 효율적인 데이터베이스의 구축이 필요하다. 본 연구에서는 스캔한 도면 이미지를 활용한 이동약자용 실내 그래프데이터베이스 구축 기법을 제안하였다. 먼저, 국내외 실내 공간 관련 표준 및 설계 기준들의 검토를 통해 이동약자의 통행과 관련된 실내 공간 및 객체, 영향 요인들을 도출하여 개념적 데이터 모델을 설계하였다. 또한, 실내의 각 공간과 시설물의 기하정보와 위상정보를 기반으로 이동약자의 접근성 및 통행 가능성을 정량화하기 위한 접근성 지수를 설계하였다. 다음으로, 스캔 도면을 입력하여 이동약자용 실내 그래프 데이터베이스 구축을 위한 프로세스를 제안하였다. 제안한 프로세스는 전이학습 기반 접근 방식을 통해 스캔 도면에서 공간의 구조 정보를 추출하고, 토폴로지 추출 및 접근성 평가를 통해 이동약자용 네트워크 모델을 생성하며, 생성한 네트워크 모델을 그래프 데이터베이스로 자동 변환하는 과정을 포함한다. 구체적으로, 제안 프로세스는 수정된 ResNet 기반의 모델을 새롭게 라벨링한 도면으로 미세 조정하여 사용함으로써 실내 구조맵을 생성한다. 이후 추출된 객체들의 공간 관계를 기반으로 각 공간을 노드와 링크로 표현한 실내 네트워크 모델을 구축한다. 각 공간의 접근성 정보는 제안된 접근성 지수와 임계값을 사용하여 생성된 후 데이터베이스에 저장되어, 이동약자를 위한 접근 가능한 그래프 추출에 활용될 수 있다. 본 연구에서는 제안한 기법을 서울대학교 도면 데이터 셋에 적용하여 이동약자용 실내 그래프 데이터베이스를 구축하고 평가하였다. 구축한 실내 그래프 데이터베이스를 활용하여 다층 경로 계획과 실내외 연계 경로 계획의 2가지 시나리오에 따라 최적 경로를 도출하였다. 그 결과, 일반 보행자의 최적 경로와 비교하여 이동약자용 최적 경로는 가까운 계단이 아닌 엘리베이터를 통한 수직 이동을 포함하였을 뿐만 아니라 접근 불가능한 공간을 회피하도록 도출되었다. 즉, 제안한 기법을 통해 이동약자 측면에서 통행 장애 정보를 포함하여 실내 환경을 적절하게 묘사하는 데이터베이스의 구축이 가능함을 확인할 수 있었다. 또한, 출입로로 명명된 관계 생성만으로 스케일이나 좌표 변환 없이 실내외 연계 경로 계획이 가능하였는데, 이는 독립적인 데이터 간 연계 사용에 적합한 그래프 데이터베이스의 특성을 반영한 결과로 판단할 수 있다. 본 연구의 주요 기여는 스캔한 도면을 사용하여 이동약자용 실내 그래프 데이터베이스를 구축하기 위한 프로세스를 개발한 것이다. 구체적으로, 이동약자의 이동에 초점을 두고 설계한 데이터 모델을 기반으로 한 데이터베이스 구축이 가능하므로 이동약자용 실내 길안내 서비스에 활용될 수 있다. 또한, 토폴로지 구축 및 그래프 데이터베이스로의 변환을 위한 하위 프로시져를 개발하였으며, 제안 프로세스는 해당 프로시져들로 구성되어 도면 입력을 통해 이동약자용 실내 그래프 데이터베이스 구축을 가능하게 한다. 해당 하위 프로시져들은 자동으로 수행될 수 있어 데이터베이스 구축 시 소요되는 시간과 비용을 절감할 수 있다. 또한, 다양한 정형 및 비정형 데이터의 연계에 적합한 그래프 데이터베이스의 특징에 의해, 제안한 프로세스를 통해 구축한 실내 데이터베이스는 기존 공간 모델의 기능을 포함하면서 다양한 유형의 길안내 서비스에 활용될 수 있을 것으로 기대된다.Changes to the indoor environment have increased social interest in ensuring the mobility of people with disabilities. Therefore, the demand for customized indoor routing services for people with mobility disabilities (PWMD), who have many travel restrictions, is increasing. These services have progressed from spatial routing to personalized routing, which reflects personal preferences and experiences in planning an optimal path. In this regard, it is necessary to generate a database for PWMD with a flexible schema suitable for the efficient manipulation and processing of data. This study aims to propose a technique of generating an indoor graph database for PWMD using scanned floor plans. First, a conceptual data model was developed by deriving relevant indoor features and influential factors, considering various international regulations on indoor environments. Also, the accessibility index was designed based on the data model to quantify the difficulties in accessing spaces based on each indoor spaces geometric characteristics. Next, a three-stage process was proposed: retrieving the structure of spaces from scanned floor plans through a transfer learning-based approach, retrieving topology and assessing accessibility for creating an indoor network model for PWMD, and converting the network model into a graph database. Specifically, an indoor structure map is created by fine-tuning the modified Resnet-based model with newly annotated floor plans for extracting structure information. Also, based on the spatial relationship of the extracted features, the indoor network model was created by abstracting indoor spaces with nodes and links. The accessibility of each space is determined by the proposed indices and thresholds; thereby, a feasible network for PWMD could be derived. Then, a process was developed for automatically converting an indoor network model, including accessibility property, into a graph database. The proposed technique was applied to the Seoul National University dataset to generate an indoor graph database for PWMD. Two scenario-based routing tests were conducted using the generated database to verify the utility of results: multi-floor routing and integrated indoor-outdoor routing. As a result, compared with the path for general pedestrians, the optimal path for PWMD was derived by avoiding inaccessible spaces, including vertical movement using elevators rather than the nearest stairs. In other words, applying the proposed technique, a database that adequately described an indoor environment in terms of PWMD with sufficient mobile constraint information could be constructed. Moreover, an integrated indoor-outdoor routing could be conducted by only creating an entrance-labeled relationship, without scale and coordinate transformation. This result reflects the usability of the generated graph database and its suitability regarding the incorporation of multiple individual data sources. The main contribution lies in the development of the process for generating an indoor graph database for PWMD using scanned floor plans. In particular, the database for PWMD routing can be generated based on the proposed data model with PWMD-related features and factors. Also, sub-procedures for topology retrieval and graph database conversion are developed to generate the indoor graph database by the end-to-end process. The developed sub-procedures are performed automatically, thereby reducing the required times and costs. It is expected that the target database of the proposed process can be generated considering utilization for various types of routing since the graph database is easily integrated with multiple types of information while covering the existing spatial models function.1. Introduction 1 1.1 Objectives and contributions 1 1.2 Related works 7 1.2.1 Indoor environment conceptualization 7 1.2.2 Indoor data construction 11 1.2.3 Accessibility assessment 19 1.3 Research scope and flow 22 2. Conceptual modeling 26 2.1 Relevant features and factors 28 2.2 Proposed data model 30 2.3 Space accessibility for PWMD 36 2.3.1 Influential factors within indoor environments 37 2.3.2 Accessibility index 41 3. Indoor graph database for PWMD from scanned floor plans 43 3.1 Retrieving structure of indoor spaces 43 3.1.1 Pre-trained model for detecting indoor geometry 45 3.1.2 Dataset with new annotation 47 3.1.3 Transfer learning-based approach 52 3.2 Generating the indoor network model for PWMD 56 3.2.1 Definition of nodes and links in the network model 60 3.2.2 The classification rule of space polygons 63 3.2.3 Connection between general spaces and doors 68 3.2.4 Node-link generation for horizontal transition spaces 71 3.2.5 Vertical link generation 75 3.2.6 Connectivity and accessibility information generation 79 3.3 Indoor graph database for PWMD 80 3.3.1 Graph representation of indoor environments 80 3.3.2 Conversion of network model into graph database 83 3.4 Entire process 87 4. Experiment and results 89 4.1 Experimental setup and test data 89 4.2 Evaluation for retrieved information 92 4.2.1 Results of structure retrieval 92 4.2.2 Results of topology retrieval 99 4.3 Generated indoor graph database for PWMD 128 4.3.1 Results of the indoor graph database for PWMD 128 4.3.2 Query-based routing 136 5. Conclusion 147 References 150 Appendix 166 국문초록 178박

Computational Framework for Parametric Modeling and Architecture-Energy Assessment of Building Floorplans

Modern building systems can be exceedingly complex. In this research we develop a computational framework for the parametric modeling and architecture-energy assessment of building floorplans. Parametric representations of floorplans are formulated as multi-layer hierarchies, with adjacent layers coupled by dependency relationships. Software is developed for two approaches to floorplan specification: (1) scripting, and (2) interactive graphical techniques. Computational procedures are developed for assessment of building code regulations, electricity cost assessment, and simplified HVAC component selection and architecture-energy sensitivity analysis. A case study analysis of a two-apartment building system is presented

On the number of rectangulations of a planar point set

AbstractWe investigate the number of different ways in which a rectangle containing a set of n noncorectilinear points can be partitioned into smaller rectangles by n (nonintersecting) segments, such that every point lies on a segment. We show that when the relative order of the points forms a separable permutation, the number of rectangulations is exactly the (n+1)st Baxter number. We also show that no matter what the order of the points is, the number of guillotine rectangulations is always the nth Schröder number, and the total number of rectangulations is O(20n/n4)

A framework for fine-grain synthesis optimization of operational amplifiers

This thesis presents a cell-level framework for Operational Amplifiers Synthesis (OASYN) coupling both circuit design and layout. For circuit design, the tool applies a corner-driven optimization, accounting for on-chip performance variations. By exploring the process, voltage, and temperature variations space, the tool extracts design worst case solution. The tool undergoes sensitivity analysis along with Pareto-optimality to achieve required specifications. For layout phase, OASYN generates a DRC proved automated layout based on a sized circuit-level description. Morata et al. (1996) introduced an elegant representation of block placement called sequence pair for general floorplans (SP). Like TCG and BSG, but unlike O-tree, B*tree, and CBL, SP is P-admissible. Unlike SP, TCG supports incremental update during operation and keeps the information of the boundary modules as well as their relative positions in the representation. Block placement algorithms that are based on SP use heuristic optimization algorithms, e.g., simulated annealing where generation of large number of sequence pairs are required. Therefore a fast algorithm is needed to generate sequence pairs after each solution perturbation. The thesis presents a new simple and efficient O(n) runtime algorithm for fast realization of incremental update for cost evaluation. The algorithm integrates sequence pair and transitive closure graph advantages into TCG-S* a superior topology update scheme which facilitates the search for optimum desired floorplan. Experiments show that TCG-S* is better than existing works in terms of area utilization and convergence speed. Routing-aware placement is implemented in OASYN, handling symmetry constraints, e.g., interdigitization, common centroid, along with congestion elimination and the enhancement of placement routability