Comparison of the Image Rejection between the Passive and the Gilbert Mixer

This paper presents a comparison of the image rejection between Gilbert mixer and the passive mixer. A simple model for mixers is set up, and the image rejection performance of passive and Gilbert mixer is analyzed based on it. Simulations and calculations were done to compare the image rejection of the two mixers. The results show that the Gilbert mixer, comparing with the passive one, shows a stronger rejection to the amplitude error of the quadrature signals at its input

CMOS Wide Tuning Gilbert Mixer with Controllable IF Bandwidth in Upcoming RF Front End for Multi-Band Multi-Standard Applications

The current global system for mobile communications, wireless local area, Bluetooth, and ultra-wideband demands a multi-band/multi-standard RF front end that can access all the available bandwidth specifications. Trade-offs occur between power consumption, noise figure, and linearity in CMOS Gilbert mixer wide tuning designs. Besides, it is preferable to have a constant IF bandwidth for different gain settings as the bandwidth varies with the load impedance when an RF receiver is tuned to a higher frequency. My dissertation consists of three parts. First, a tunable constant IF bandwidth Gilbert mixer is introduced for multi-band standard wireless applications such as 802.11 a/b/g WLAN and 802.16a WMAN, followed by a design synthesis approach to optimize the mixer to meet the design center frequency range, constant IF bandwidth, and power. A synthesized Gilbert mixer with effective prototype inductors, designed in 180 nm CMOS process, is presented in this dissertation with the tunability of 200 MHz IF, a constant IF bandwidth of 50 MHz, a conversion gain of 13.75 dB, a noise figure of 2.9dB, 1-dB compression point of -15.19 dBm, IIP3 of -5.8 dBm, and a power of 9 mW. Next, mixer inductor loss and equivalent electronic circuit analysis are presented to optimize the approach to offset center frequency and bandwidth inaccuracy due to the inductance loss between the actual and ideal prototype inductor. The proposed tunable Gilbert mixer simulations present a tunable IF of 177.8 MHz, an IF bandwidth of 87.57 MHz, a conversion gain of 7.4 dB, a noise figure of 3.14 dB, 1-dB compression point of -17.1 dBm, and IIP3 of -19.8 dBm. Last, a CMOS integrated wide frequency span CMOS low noise amplifier is integrated with the tunable Gilbert mixer to achieve a 27.68 dB conversion gain, a 3.47 dB low noise figure, -14.6 dBm 1-dB compression point, and -18.6 dBm IIP3

High Dynamic Range RF Front End with Noise Cancellation and Linearization for WiMAX Receivers

This research deals with verification of the high dynamic range for a heterodyne radio frequency (RF) front end. A 2.6 GHz RF front end is designed and implemented in a hybrid microwave integrated circuit (HMIC) for worldwide interoperability for microwave access (WiMAX) receivers. The heterodyne RF front end consists of a low-noise amplifier (LNA) with noise cancellation, an RF bandpass filter (BPF), a downconverter with linearization, and an intermediate frequency (IF) BPF. A noise canceling technique used in the low-noise amplifier eliminates a thermal noise and then reduces the noise figure (NF) of the RF front end by 0.9 dB. Use of a downconverter with diode linearizer also compensates for gain compression, which increases the input-referred third-order intercept point (IIP3) of the RF front end by 4.3 dB. The proposed method substantially increases the spurious-free dynamic range (DRf) of the RF front end by 3.5 dB

Multi-Gigabit Wireless data transfer at 60 GHz

In this paper we describe the status of the first prototype of the 60 GHz wireless Multi-gigabit data transfer topology currently under development at University of Heidelberg using IBM 130 nm SiGe HBT BiCMOS technology. The 60 GHz band is very suitable for high data rate and short distance applications as for example needed in the HEP experments. The wireless transceiver consist of a transmitter and a receiver. The transmitter includes an On-Off Keying (OOK) modulator, an Local Oscillator (LO), a Power Amplifier (PA) and a BandPass Filter (BPF). The receiver part is composed of a BandPass- Filter (BPF), a Low Noise Amplifier (LNA), a double balanced down-convert Gilbert mixer, a Local Oscillator (LO), then a BPF to remove the mixer introduced noise, an Intermediate Amplifier (IF), an On-Off Keying demodulator and a limiting amplifier. The first prototype would be able to handle a data-rate of about 3.5 Gbps over a link distance of 1 m. The first simulations of the LNA show that a Noise Figure (NF) of 5 dB, a power gain of 21 dB at 60 GHz with a 3 dB bandwidth of more than 20 GHz with a power consumption 11 mW are achieved. Simulations of the PA show an output referred compression point P1dB of 19.7 dB at 60 GHz.Comment: Proceedings of the WIT201

Wideband Monolithic Microwave Integrated Circuit Frequency Converters with GaAs mHEMT Technology

We present monolithic microwave integrated circuit (MMIC) frequency converter, which can be used for up and down conversion, due to the large RF and IF port bandwidth. The MMIC converters are based on commercially available GaAs mHEMT technology and are comprised of a Gilbert mixer cell core, baluns and combiners. Single ended and balanced configurations DC and AC coupled have been investigated. The instantaneous 3 dB bandwidth at both the RF and the IF port of the frequency converters is ∼ 20 GHz with excellent amplitude and phase linearity. The predicted conversion gain is around 10 dB. Simulated results are supported by experimental characterization. Good agreement is found between simulations and experiment is found after adjustment of technology parameters

A 0.8 V T Network-Based 2.6 GHz Downconverter RFIC

A 2.6 GHz downconverter RFIC is designed and implemented using a 0.18 μm CMOS standard process. An important goal of the design is to achieve the high linearity that is required in WiMAX systems with a low supply voltage. A passive T phase-shift network is used as an RF input stage in a Gilbert cell to reduce supply voltage. A single supply voltage of 0.8 V is used with a power consumption of 5.87 mW. The T network-based downconverter achieves a conversion gain (CG) of 5 dB, a single-sideband noise figure (NF) of 16.16 dB, an RF-to-IF isolation of greater than 20 dB, and an input-referred third-order intercept point (IIP3) of 1 dBm when the LO power of -13 dBm is applied

A Direct Carrier I/Q Modulator for High-Speed Communication at D-Band Using 130 nm SiGe BiCMOS Technology

This paper presents a 110-170 GHz direct conversion I/Q modulator realized in 130 nm SiGe BiCMOS technology with ft/fmax values of 250 GHz/ 370 GHz. The design is based on double-balanced Gilbert mixer cells with on-chip quadrature LO phase shifter and RF balun. In single-sideband operation, the modulator exhibits up to 9.5 dB conversion gain and has measured 3 dB IF bandwidth of 12 GHz. The measured image rejection ratio and LO to RF isolation are as high as 20 dB and 31 dB respectively. Meas-ured input P1dB is -17 dBm at 127 GHz output. The DC power con-sumption is 53 mW. The active chip area is 620 μm× 480 μm in-cluding the RF and LO baluns. The circuit is capable of transmit-ting more than 12 Gbit/s QPSK signal

Designing of Low Power RF-Receiver Front-end with CMOS Technology

This thesis studies how to design ultra low power radio-receiver front-end circuit consisting of a low-noise CMOS amplifier and mixer for low power Bluetooth applications. This system is designed in 65-nm CMOS technology with the voltage source of 1.2 V, and it operates at 2.4 GHz. This research project includes the design of radio frequency integrated circuit with CMOS technology using CAD software for circuit design, layout design, pre and post-layout simulations. Firstly, brief study about both Low noise amplifier (LNA) and mixer has been done, and then the design structure such as, input matching network of LNA, noise of system, gain and linearity have been discussed. Later, next section reports simulation results of LNA, mixer and eventually their combination. Furthermore, the effect of packaging and non-ideal on-chip circuit performance has been considered and shown in comparison tables for more clarity. Finally, after the layout design, the obtained results of both post-layout and pre-layout simulations are compared and shown the stability of the design with parasitics consideration

A 2.4GHz 830pJ/bit duty-cycled wake-up receiver with −82dBm sensitivity for crystal-less wireless sensor nodes

A 65 nm CMOS 2.4 GHz wake-up receiver operating with low-accuracy frequency references has been realized. Robustness to frequency inaccuracy is achieved by employing non-coherent energy detection, broadband-IF heterodyne architecture and impulse-radio modulation. The radio dissipates 415 ¿W at 500 kb/s and achieves a sensitivity of -82 dBm with an energy efficiency of 830 pJ/bit.\u

Design and Simulate Radio Frequency (RF) CMOS Mixer Circuit

Radio frequency design has been one of the principal research areas in the· recent past. Much of work has been done in integrating data with wireless communication. Since a decade ago, the frequencies for such communication have been in free bands available in the low frequency spectrum like 900 MHz and lower. With rapid improvement in the technology of microelectronic nowadays, these frequency spectrums are improved to be within the range of ultra band frequencies of GHz. These emergences of several RF Wireless Communication standards of communication have demanded availability of low cost analogue blocks for use in transceiver. Despite rigorous research undergoing, it has been difficult to meet the design specification by low cost technologies like CMOS. In this project, the presented mixer down converts Radio Frequency (RF) of 1.8 GHz to 200 MHz which typifies specifications for a GSM 1800 receiver with Voltage Conversion Gain (VCG) of 7.703 dB, IIP3 of 10.916 dBm and Noise Figure (NF) of 11.094 dB with current utilization of 6 rnA. This hi.gh conversion gain and low noise figure mixer is achieved by utilizing Differential Gilbert Mixer Cell. The mixer was simulated in analogue environment of Spectra Cadence Schematic