Hysteresis-Free Nanosecond Pulsed Electrical Characterization of Top-Gated Graphene Transistors

We measure top-gated graphene field effect transistors (GFETs) with nanosecond-range pulsed gate and drain voltages. Due to high-k dielectric or graphene imperfections, the drain current decreases ~10% over time scales of ~10 us, consistent with charge trapping mechanisms. Pulsed operation leads to hysteresis-free I-V characteristics, which are studied with pulses as short as 75 ns and 150 ns at the drain and gate, respectively. The pulsed operation enables reliable extraction of GFET intrinsic transconductance and mobility values independent of sweep direction, which are up to a factor of two higher than those obtained from simple DC characterization. We also observe drain-bias-induced charge trapping effects at lateral fields greater than 0.1 V/um. In addition, using modeling and capacitance-voltage measurements we extract charge trap densities up to 10^12 1/cm^2 in the top gate dielectric (here Al2O3). Our study illustrates important time- and field-dependent imperfections of top-gated GFETs with high-k dielectrics, which must be carefully considered for future developments of this technologyComment: to appear in IEEE Transactions on Electron Devices (2014

Application and evaluation of the RF charge-pumping technique

In this paper, we will discuss the extendibility of the charge-pumping (CP) technique toward frequencies up to 4 GHz. Such high frequencies are attractive when a significant gate leakage current flows, obscuring the CP current at lower pumping frequencies.\ud It is shown that using RF gate excitation, accurate CP curves can be obtained on MOS devices with a leakage current density exceeding 1 A•cm−2 . A theoretical analysis of the trap response to RF gate voltage signals is presented, giving a clear insight on the benefits and limitations of the technique.\u

MIS capacitor studies on silicon carbide single crystals

Cubic SIC metal-insulator-semiconductor (MIS) capacitors with thermally grown or chemical-vapor-deposited (CVD) insulators were characterized by capacitance-voltage (C-V), conductance-voltage (G-V), and current-voltage (I-V) measurements. The purpose of these measurements was to determine the four charge densities commonly present in an MIS capacitor (oxide fixed charge, N(f); interface trap level density, D(it); oxide trapped charge, N(ot); and mobile ionic charge, N(m)) and to determine the stability of the device properties with electric-field stress and temperature. The section headings in the report include the following: Capacitance-voltage and conductance-voltage measurements; Current-voltage measurements; Deep-level transient spectroscopy; and Conclusions (Electrical characteristics of SiC MIS capacitors)

Dielectric relaxation and Charge trapping characteristics study in Germanium based MOS devices with HfO2 /Dy2O3 gate stacks

In the present work we investigate the dielectric relaxation effects and charge trapping characteristics of HfO2 /Dy2O3 gate stacks grown on Ge substrates. The MOS devices have been subjected to constant voltage stress (CVS) conditions at accumulation and show relaxation effects in the whole range of applied stress voltages. Applied voltage polarities as well as thickness dependence of the relaxation effects have been investigated. Charge trapping is negligible at low stress fields while at higher fields (>4MV/cm) it becomes significant. In addition, we give experimental evidence that in tandem with the dielectric relaxation effect another mechanism- the so-called Maxwell-Wagner instability- is present and affects the transient current during the application of a CVS pulse. This instability is also found to be field dependent thus resulting in a trapped charge which is negative at low stress fields but changes to positive at higher fields.Comment: 27pages, 10 figures, 3 tables, regular journal contribution (accepted in IEEE TED, Vol.50, issue 10

Si-SiO2 interface behavior in n-MOSFETs with screening potential during high-field injection

This work investigates the screening of hot carrier stress degradation in n-channel MOSFETs when the devices were exposed to plasma processing. Devices with various antenna ratios were subjected to current stress (both gate injection and substrate injection) while the source and drain terminals were reverse biased by a screening potential followed by hot carrier stress. It was observed that screening of the drain edge was effective for both gate injection and substrate injection at different screening potentials. The hot carrier lifetime is directly related to interface state density (Dit), measured by charge pumping method. The results suggest that hot electron degradation could be severe or mild for devices affected by plasma damage depending on their exposure to the level of screening potential. This work also investigates the screening of Si-H bond concentration for polarity-dependent high field electron injection under effective screening potentials. It was observed that Si-H bond concentration varies based on the screening of the source and the drain edges during current stress when a reverse bias potential is applied to the source and drain terminals. The interface state density (Dit), measured by charge pumping method, is found to have strong dependence on the concentration of the Si-H bonds. Hot carrier stress that significantly contributes to Si-H bond breaking confirmed the effective screening. The results also indicate that Si-H bond breaking mechanism during screening is dependent on the polarity of the current stress and the screening potential applied

Negative Bias Temperature Instability And Charge Trapping Effects On Analog And Digital Circuit Reliability

Nanoscale p-channel transistors under negative gate bias at an elevated temperature show threshold voltage degradation after a short period of stress time. In addition, nanoscale (45 nm) n-channel transistors using high-k (HfO2) dielectrics to reduce gate leakage power for advanced microprocessors exhibit fast transient charge trapping effect leading to threshold voltage instability and mobility reduction. A simulation methodology to quantify the circuit level degradation subjected to negative bias temperature instability (NBTI) and fast transient charge trapping effect has been developed in this thesis work. Different current mirror and two-stage operation amplifier structures are studied to evaluate the impact of NBTI on CMOS analog circuit performances for nanoscale applications. Fundamental digital circuit such as an eleven-stage ring oscillator has also been evaluated to examine the fast transient charge transient effect of HfO2 high-k transistors on the propagation delay of ring oscillator performance. The preliminary results show that the negative bias temperature instability reduces the bandwidth of CMOS operating amplifiers, but increases the amplifier\u27s voltage gain at mid-frequency range. The transient charge trapping effect increases the propagation delay of ring oscillator. The evaluation methodology developed in this thesis could be extended to study other CMOS device and circuit reliability issues subjected to electrical and temperature stresses

Negative Bias Temperature Instability And Charge Trapping Effects On Analog And Digital Circuit Reliability

Nanoscale p-channel transistors under negative gate bias at an elevated temperature show threshold voltage degradation after a short period of stress time. In addition, nanoscale (45 nm) n-channel transistors using high-k (HfO2) dielectrics to reduce gate leakage power for advanced microprocessors exhibit fast transient charge trapping effect leading to threshold voltage instability and mobility reduction. A simulation methodology to quantify the circuit level degradation subjected to negative bias temperature instability (NBTI) and fast transient charge trapping effect has been developed in this thesis work. Different current mirror and two-stage operation amplifier structures are studied to evaluate the impact of NBTI on CMOS analog circuit performances for nanoscale applications. Fundamental digital circuit such as an eleven-stage ring oscillator has also been evaluated to examine the fast transient charge transient effect of HfO2 high-k transistors on the propagation delay of ring oscillator performance. The preliminary results show that the negative bias temperature instability reduces the bandwidth of CMOS operating amplifiers, but increases the amplifier\u27s voltage gain at mid-frequency range. The transient charge trapping effect increases the propagation delay of ring oscillator. The evaluation methodology developed in this thesis could be extended to study other CMOS device and circuit reliability issues subjected to electrical and temperature stresses

Defect Induced Aging and Breakdown in High-k Dielectrics

abstract: High-k dielectrics have been employed in the metal-oxide semiconductor field effect transistors (MOSFETs) since 45 nm technology node. In this MOSFET industry, Moore’s law projects the feature size of MOSFET scales half within every 18 months. Such scaling down theory has not only led to the physical limit of manufacturing but also raised the reliability issues in MOSFETs. After the incorporation of HfO2 based high-k dielectrics, the stacked oxides based gate insulator is facing rather challenging reliability issues due to the vulnerable HfO2 layer, ultra-thin interfacial SiO2 layer, and even messy interface between SiO2 and HfO2. Bias temperature instabilities (BTI), hot channel electrons injections (HCI), stress-induced leakage current (SILC), and time dependent dielectric breakdown (TDDB) are the four most prominent reliability challenges impacting the lifetime of the chips under use. In order to fully understand the origins that could potentially challenge the reliability of the MOSFETs the defects induced aging and breakdown of the high-k dielectrics have been profoundly investigated here. BTI aging has been investigated to be related to charging effects from the bulk oxide traps and generations of Si-H bonds related interface traps. CVS and RVS induced dielectric breakdown studies have been performed and investigated. The breakdown process is regarded to be related to oxygen vacancies generations triggered by hot hole injections from anode. Post breakdown conduction study in the RRAM devices have shown irreversible characteristics of the dielectrics, although the resistance could be switched into high resistance state.Dissertation/ThesisDoctoral Dissertation Electrical Engineering 201