Predicting power scalability in a reconfigurable platform

This thesis focuses on the evolution of digital hardware systems. A reconfigurable platform is proposed and analysed based on thin-body, fully-depleted silicon-on-insulator Schottky-barrier transistors with metal gates and silicide source/drain (TBFDSBSOI). These offer the potential for simplified processing that will allow them to reach ultimate nanoscale gate dimensions. Technology CAD was used to show that the threshold voltage in TBFDSBSOI devices will be controllable by gate potentials that scale down with the channel dimensions while remaining within appropriate gate reliability limits. SPICE simulations determined that the magnitude of the threshold shift predicted by TCAD software would be sufficient to control the logic configuration of a simple, regular array of these TBFDSBSOI transistors as well as to constrain its overall subthreshold power growth. Using these devices, a reconfigurable platform is proposed based on a regular 6-input, 6-output NOR LUT block in which the logic and configuration functions of the array are mapped onto separate gates of the double-gate device. A new analytic model of the relationship between power (P), area (A) and performance (T) has been developed based on a simple VLSI complexity metric of the form ATσ = constant. As σ defines the performance “return” gained as a result of an increase in area, it also represents a bound on the architectural options available in power-scalable digital systems. This analytic model was used to determine that simple computing functions mapped to the reconfigurable platform will exhibit continuous power-area-performance scaling behavior. A number of simple arithmetic circuits were mapped to the array and their delay and subthreshold leakage analysed over a representative range of supply and threshold voltages, thus determining a worse-case range for the device/circuit-level parameters of the model. Finally, an architectural simulation was built in VHDL-AMS. The frequency scaling described by σ, combined with the device/circuit-level parameters predicts the overall power and performance scaling of parallel architectures mapped to the array

Novel dual-threshold voltage FinFETs for circuit design and optimization

A great research effort has been invested on finding alternatives to CMOS that have better process variation and subthreshold leakage. From possible candidates, FinFET is the most compatible with respect to CMOS and it has shown promising leakage and speed performance. This thesis introduces basic characteristics of FinFETs and the effects of FinFET physical parameters on their performance are explained quantitatively. I show how dual- V th independent-gate FinFETs can be fabricated by optimizing their physical parameters. Optimum values for these physical parameters are derived using the physics-based University of Florida SPICE model for double-gate devices, and the optimized FinFETs are simulated and validated using Sentaurus TCAD simulations. Dual-14, FinFETs with independent gates enable series and parallel merge transformations in logic gates, realizing compact low power alternative gates with competitive performance and reduced input capacitance in comparison to conventional FinFET gates. Furthermore, they also enable the design of a new class of compact logic gates with higher expressive power and flexibility than CMOS gates. Synthesis results for 16 benchmark circuits from the ISCAS and OpenSPARC suites indicate that on average at 2GHz and 75°C, the library that contains the novel gates reduces total power and the number of fins by 36% and 37% respectively, over a conventional library that does not have novel gates in the 32nm technology

Robust Optimization of Nanometer SRAM Designs

Technology scaling has been the most obvious choice of designers and chip manufacturing companies to improve the performance of analog and digital circuits. With the ever shrinking technological node, process variations can no longer be ignored and play a significant role in determining the performance of nanoscaled devices. By choosing a worst case design methodology, circuit designers have been very munificent with the design parameters chosen, often manifesting in pessimistic designs with significant area overheads. Significant work has been done in estimating the impact of intra-die process variations on circuit performance, pertinently, noise margin and standby leakage power, for fixed transistor channel dimensions. However, for an optimal, high yield, SRAM cell design, it is absolutely imperative to analyze the impact of process variations at every design point, especially, since the distribution of process variations is a statistically varying parameter and has an inverse correlation with the area of the MOS transistor. Furthermore, the first order analytical models used for optimization of SRAM memories are not as accurate and the impact of voltage and its inclusion as an input, along with other design parameters, is often ignored. In this thesis, the performance parameters of a nano-scaled 6-T SRAM cell are modeled as an accurate, yield aware, empirical polynomial predictor, in the presence of intra-die process variations. The estimated empirical models are used in a constrained non-linear, robust optimization framework to design an SRAM cell, for a 45 nm CMOS technology, having optimal performance, according to bounds specified for the circuit performance parameters, with the objective of minimizing on-chip area. This statistically aware technique provides a more realistic design methodology to study the trade off between performance parameters of the SRAM. Furthermore, a dual optimization approach is followed by considering SRAM power supply and wordline voltages as additional input parameters, to simultaneously tune the design parameters, ensuring a high yield and considerable area reduction. In addition, the cell level optimization framework is extended to the system level optimization of caches, under both cell level and system level performance constraints

DOWNSCALING OF 0.25uM TO O.13uM NMOS USING SILVACO SOFTWARE WITH DIFFERENT SUBMICRON TECHNOLOGY

For the last three decades, MOS device technologies have been improved due to downscaling. It consumes less power, have shorter delay and occupy less space. The CMOS comprises of p-type and n-type, has become the main growth of miniaturization microelectronics industry. In this project, ATHENA andATLAS are simulators used with the objective to downscale 0.25um to 0.13um NMOS using two different recipes and to obtain its electrical characteristic. Ascaling factor, a of 1.923 is utilized. Three factors are investigated; the gate length (Lg), gate oxide thickness (U) and threshold voltage (Vth) adjust implant. The parameters evaluated include W, Vth and saturation current (WO as well as ID-VD, Id-Vg and subthreshold current (St) curve. After downscaling to 0.13um, both recipes haveWvalues of3.36nm while the Vth obtain are 0.31V and 0.37V respectively. The W value is 343uA/um and 519uA/um while the St is 65mV/dec and 128mV/dec respectively. Each recipe has its own drawback. First recipe has lower Id^ and lower St while second recipe has higher IDsat and higher St Higher W means the device can perform at taster speed while lower St. shows the device has good turn-off characteristics. Overall, the electrical parameters obtained are agreeable with ITRS requirement and other reported works except for the result ofW This could be due to the direct scaling. Other parameters such as St could not be compared as itis confidential to the public

DOWNSCALING OF 0.25|iM TO O.ttpM NMOS USING SILVACO SOFTWARE WITH DIFFERENT SUBMICRON TECHNOLOGY

For the last three decades, MOS device technologies have been improved due to downscaling. It consumes less power, have shorter delay and occupy less space. The CMOS comprises of p-type and n-type, has become the main growth of miniaturization microelectronics industry. In this project, ATHENA andATLAS are simulators used with the objective to downscale 0.25um to 0.13um NMOS using two different recipes and to obtain its electrical characteristic. Ascaling factor, a of 1.923 is utilized. Three factors are investigated; the gate length (Lg), gate oxide thickness (U) and threshold voltage (Vth) adjust implant. The parameters evaluated include W, Vth and saturation current (WO as well as ID-VD, Id-Vg and subthreshold current (St) curve. After downscaling to 0.13um, both recipes haveWvalues of3.36nm while the Vth obtain are 0.31V and 0.37V respectively. The W value is 343uA/um and 519uA/um while the St is 65mV/dec and 128mV/dec respectively. Each recipe has its own drawback. First recipe has lower Id^ and lower St while second recipe has higher IDsat and higher St Higher W means the device can perform at taster speed while lower St. shows the device has good turn-off characteristics. Overall, the electrical parameters obtained are agreeable with ITRS requirement and other reported works except for the result ofW This could be due to the direct scaling. Other parameters such as St could not be compared as itis confidential to the public

Low-Power and Programmable Analog Circuitry for Wireless Sensors

Embedding networks of secure, wirelessly-connected sensors and actuators will help us to conscientiously manage our local and extended environments. One major challenge for this vision is to create networks of wireless sensor devices that provide maximal knowledge of their environment while using only the energy that is available within that environment. In this work, it is argued that the energy constraints in wireless sensor design are best addressed by incorporating analog signal processors. The low power-consumption of an analog signal processor allows persistent monitoring of multiple sensors while the device\u27s analog-to-digital converter, microcontroller, and transceiver are all in sleep mode. This dissertation describes the development of analog signal processing integrated circuits for wireless sensor networks. Specific technology problems that are addressed include reconfigurable processing architectures for low-power sensing applications, as well as the development of reprogrammable biasing for analog circuits

Variability-aware low-power techniques for nanoscale mixed-signal circuits.

New circuit design techniques that accommodate lower supply voltages necessary for portable systems need to be integrated into the semiconductor intellectual property (IP) core. Systems that once worked at 3.3 V or 2.5 V now need to work at 1.8 V or lower, without causing any performance degradation. Also, the fluctuation of device characteristics caused by process variation in nanometer technologies is seen as design yield loss. The numerous parasitic effects induced by layouts, especially for high-performance and high-speed circuits, pose a problem for IC design. Lack of exact layout information during circuit sizing leads to long design iterations involving time-consuming runs of complex tools. There is a strong need for low-power, high-performance, parasitic-aware and process-variation-tolerant circuit design. This dissertation proposes methodologies and techniques to achieve variability, power, performance, and parasitic-aware circuit designs. Three approaches are proposed: the single iteration automatic approach, the hybrid Monte Carlo and design of experiments (DOE) approach, and the corner-based approach. Widely used mixed-signal circuits such as analog-to-digital converter (ADC), voltage controlled oscillator (VCO), voltage level converter and active pixel sensor (APS) have been designed at nanoscale complementary metal oxide semiconductor (CMOS) and subjected to the proposed methodologies. The effectiveness of the proposed methodologies has been demonstrated through exhaustive simulations. Apart from these methodologies, the application of dual-oxide and dual-threshold techniques at circuit level in order to minimize power and leakage is also explored

Low-Power and Programmable Analog Circuitry for Wireless Sensors

Embedding networks of secure, wirelessly-connected sensors and actuators will help us to conscientiously manage our local and extended environments. One major challenge for this vision is to create networks of wireless sensor devices that provide maximal knowledge of their environment while using only the energy that is available within that environment. In this work, it is argued that the energy constraints in wireless sensor design are best addressed by incorporating analog signal processors. The low power-consumption of an analog signal processor allows persistent monitoring of multiple sensors while the device\u27s analog-to-digital converter, microcontroller, and transceiver are all in sleep mode. This dissertation describes the development of analog signal processing integrated circuits for wireless sensor networks. Specific technology problems that are addressed include reconfigurable processing architectures for low-power sensing applications, as well as the development of reprogrammable biasing for analog circuits

Development and modeling of a low temperature thin-film CMOS on glass

The push to develop integrated systems using thin-film transistors (TFT) on insulating substrates (i.e. glass) has always been limited due to low-mobility semiconducting films such as amorphous and polycrystalline silicon. Corning Incorporated is developing a new substrate material known as silicon-on-glass (SiOG). It is intrinsically better than amorphous and polycrystalline silicon materials due to its single crystal nature of the silicon film. This however does not mitigate the challenges associated with low temperature CMOS process and fabrication. The first generation of TFTs fabricated at RIT showed the potential of SiOG as a viable substrate material, but were plagued by considerable short comings such as high leakage and low transconductance. As part of this study, refinements to TFT processing on SiOG have demonstrated significant improvement to TFT performance and uniformity, showing increase transconductanace/mobility, lower subthreshold swing, tighter VT distributions, and near symmetrical NFET and PFET operation about 0 V. With these improvements minimal steps have been added to the manufacturing process, keeping simple and adoptable by the flat panel display (FPD) industry. Device modeling clearly demonstrates the key areas important to electrical operation, such as dopant activation, interface charge/trap reduction, and workfunction engineering. It addition, modeling and simulation have helped to explain the governing physics of device operation explaining non-ideal effects such as gate induced drain leakage (GIDL) and various mobility degradation mechanism. An overview of device design, process refinements and device operation is presented. Process modifications and resulting benefits are discussed along with CMOS integration on SiOG

Unreliable Silicon: Circuit through System-Level Techniques for Mitigating the Adverse Effects of Process Variation, Device Degradation and Environmental Conditions.

Designing and manufacturing integrated circuits in advanced, highly-scaled processing technologies that meet stringent specification sets is an increasingly unreliable proposition. Dimensional processing variations, time and stress dependent device degradation and potentially varying environmental conditions exacerbate deviations in performance, power and even functionality of integrated circuits. This work explores a system-level adaptive design philosophy intended to mitigate the power and performance impact of unreliable silicon devices and presents enabling circuits for SRAM variation mitigation and in-situ measurement of device degradation in 130nm and 45nm processing technologies. An adaptation of RAZOR-based DVS designed for on-chip memory power reduction and reliability lifetime improvement enables the elimination of 250 mV of voltage margin in a 1.8V design, with up to 500 mV of reduction when allowing 5% of memory operations to use multiple cycles. A novel PID-controlled dynamic reliability management (DRM) system is presented, allowing user-specified circuit lifetime to be dynamically managed via dynamic voltage and frequency scaling. Peak performance improvement of 20-35% is achievable in typical processing systems by allowing brief periods of elevated voltage operation through the real-time DRM system, while minimizing voltage during non-critical periods of operation to maximize circuit lifetime. A probabilistic analysis of oxide breakdown using the percolation model indicates the need for 1000-2000 integrated in-situ sensors to achieve oxide lifetime prediction error at or under 10%. The conclusions from the oxide analysis are used to guide the design of a series of novel on-chip reliability monitoring circuits for use in a real-time DRM system. A 130nm in-situ oxide breakdown measurement sensor presented is the first published design of an oxide-breakdown oriented circuit and is compatible with standard-cell style automatic “place and route” design styles used in the majority of application specific integrated circuit designs. Measured results show increases in gate oxide leakage of 14-35% after accelerated stress testing. A second generation design of the on-chip oxide degradation sensor is presented that reduces stress mode power consumption by 111,785X over the initial design while providing an ideal 1:1 mapping of gate leakage to output frequency in extracted simulations.Ph.D.Electrical EngineeringUniversity of Michigan, Horace H. Rackham School of Graduate Studieshttp://deepblue.lib.umich.edu/bitstream/2027.42/60701/1/ekarl_1.pd