1,001 research outputs found
Dynamic Field Programmable Logic-Driven Soft Exosuit
The next generation of etextiles foresees an era of smart wearable garments
where embedded seamless intelligence provides the ability to sense, process and
perform. Core to this vision is embedded textile functionality enabling dynamic
configuration. In this paper we detail a methodology, design and implementation
of a dynamic field programmable logic-driven fabric soft exosuit. Dynamic field
programmability allows the soft exosuit to alter its functionality and adapt to
specific exercise programs depending on the wearers need. The dynamic field
programmability is enabled through motion based control arm movements of the
soft exosuit triggering momentary sensors embedded in the fabric exosuit at
specific joint placement points (right arm: wrist, elbow).The embedded
circuitry in the fabric exosuit is implemented using a layered and
interchangeable approach. This includes logic gate patches (AND,OR,NOT) and a
layered textile interconnection panel. This modular and interchangeable design
enhances the soft exosuits flexibility and adaptability. A truth table aligning
to a rehabilitation healthcare use case was utilised. Tests were completed
validating the field programmability of the soft exosuit and its capability to
switch between its embedded logic driven circuitry and its operational and
functionality options controlled by motion movement of the wearers right arm
(elbow and wrist). Iterative exercise movement and acceleration based tests
were completed to validate the functionality of the field programmable logic
driven fabric exosuit. We demonstrate a working soft exosuit prototype with
motion controlled operational functionality that can be applied to
rehabilitation applications.Comment: 20 pages, 9 figure
Techniques for the realization of ultra- reliable spaceborne computer Final report
Bibliography and new techniques for use of error correction and redundancy to improve reliability of spaceborne computer
Synthesis and Optimization of Reversible Circuits - A Survey
Reversible logic circuits have been historically motivated by theoretical
research in low-power electronics as well as practical improvement of
bit-manipulation transforms in cryptography and computer graphics. Recently,
reversible circuits have attracted interest as components of quantum
algorithms, as well as in photonic and nano-computing technologies where some
switching devices offer no signal gain. Research in generating reversible logic
distinguishes between circuit synthesis, post-synthesis optimization, and
technology mapping. In this survey, we review algorithmic paradigms ---
search-based, cycle-based, transformation-based, and BDD-based --- as well as
specific algorithms for reversible synthesis, both exact and heuristic. We
conclude the survey by outlining key open challenges in synthesis of reversible
and quantum logic, as well as most common misconceptions.Comment: 34 pages, 15 figures, 2 table
CAD Tools for Synthesis of Sleep Convention Logic
This dissertation proposes an automated flow for the Sleep Convention Logic (SCL) asynchronous design style. The proposed flow synthesizes synchronous RTL into an SCL netlist. The flow utilizes commercial design tools, while supplementing missing functionality using custom tools. A method for determining the performance bottleneck in an SCL design is proposed. A constraint-driven method to increase the performance of linear SCL pipelines is proposed. Several enhancements to SCL are proposed, including techniques to reduce the number of registers and total sleep capacitance in an SCL design
Quantum-dot Cellular Automata: Review Paper
Quantum-dot Cellular Automata (QCA) is one of the most important discoveries that will be the successful alternative for CMOS technology in the near future. An important feature of this technique, which has attracted the attention of many researchers, is that it is characterized by its low energy consumption, high speed and small size compared with CMOS. Inverter and majority gate are the basic building blocks for QCA circuits where it can design the most logical circuit using these gates with help of QCA wire. Due to the lack of availability of review papers, this paper will be a destination for many people who are interested in the QCA field and to know how it works and why it had taken lots of attention recentl
Asynchronous Logic Circuits and Sheaf Obstructions
AbstractThis article exhibits a particular encoding of logic circuits into a sheaf formalism. The central result of this article is that there exists strictly more information available to a circuit designer in this setting than exists in static truth tables, but less than exists in event-level simulation. This information is related to the timing behavior of the logic circuits, and thereby provides a “bridge” between static logic analysis and detailed simulation
Research in the effective implementation of guidance computers with large scale arrays Interim report
Functional logic character implementation in breadboard design of NASA modular compute
Design and Analysis of an Adaptive Asynchronous System Architecture for Energy Efficiency
Power has become a critical design parameter for digital CMOS integrated circuits. With performance still garnering much concern, a central idea has emerged: minimizing power consumption while maintaining performance. The use of dynamic voltage scaling (DVS) with parallelism has shown to be an effective way of saving power while maintaining performance. However, the potency of DVS and parallelism in traditional, clocked synchronous systems is limited because of the strict timing requirements such systems must comply with. Delay-insensitive (DI) asynchronous systems have the potential to benefit more from these techniques due to their flexible timing requirements and high modularity. This dissertation presents the design and analysis of a real-time adaptive DVS architecture for paralleled Multi-Threshold NULL Convention Logic (MTNCL) systems. Results show that energy-efficient systems with low area overhead can be created using this approach
Fault and Defect Tolerant Computer Architectures: Reliable Computing With Unreliable Devices
This research addresses design of a reliable computer from unreliable device technologies. A system architecture is developed for a fault and defect tolerant (FDT) computer. Trade-offs between different techniques are studied and yield and hardware cost models are developed. Fault and defect tolerant designs are created for the processor and the cache memory. Simulation results for the content-addressable memory (CAM)-based cache show 90% yield with device failure probabilities of 3 x 10(-6), three orders of magnitude better than non fault tolerant caches of the same size. The entire processor achieves 70% yield with device failure probabilities exceeding 10(-6). The required hardware redundancy is approximately 15 times that of a non-fault tolerant design. While larger than current FT designs, this architecture allows the use of devices much more likely to fail than silicon CMOS. As part of model development, an improved model is derived for NAND Multiplexing. The model is the first accurate model for small and medium amounts of redundancy. Previous models are extended to account for dependence between the inputs and produce more accurate results
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