Analytical Modeling of Ultrashort-Channel MOS Transistors

Les geometries de transistors d'avui són al rang de nanòmetres d'un sol dígit. En conseqüència, les funcionalitats dels dispositius es veuen afectades negativament pels efectes de canal curt i de mecànica quàntica (SCE i QMEs). Una transició de la geometria del transistor d'efecte de camp de tipus FinFET a Gate-All-Around (GAA) FETs com FETs de nanofils cilíndrics (NW) i de nanoplaques de silici (SiNS) es preveuen en els propers nodes tecnològics per suprimir els SCE i garantir una major miniaturització del MOSFET Aquesta dissertació se centra en el modelat analític de FETs de tipus NW i SiNS de canal ultracurt.S'introdueix un concepte de dimensions de doble porta (DG) equivalent per transferir un model de potencial de DG analític a FET de NW. Un model de corrent de DG compacte es modifica aprofitant la simetria rotacional dels FET de NW. L'efecte del confinament quàntic (QC) és implementat considerant l'eixamplament addicional de la banda prohibida al càlcul d'una concentració de portadors de càrrega intrínseca efectiva i al càlcul del voltatge llindar. L'efecte de corrent túnel directe de font a drenador (DSDT) a SiNS FET ultraescalats es modela amb el nou mètode de wavelets. Aquest model calcula analíticament la probabilitat de tunelització per a cada energia de l'electró, aproximant la forma de la barrera potencial mitjançant una barrera rectangular amb una altura de barrera equivalent. A causa de la fórmula de corrent túnel de Tsu-Esaki no analíticament integrable, es presenta un mètode analític anomenat model quasi-compacte (QCM). Aquest enfocament requereix, entre altres aproximacions, una iteració de Newton i una interpolació lineal de la densitat de corrent amb efecte túnel. A més, es realitza una anàlisi criogènica de temperatura i dopatge. S'investiga la forta influència de la distància del nivell de Fermi a la font des de la vora de la banda de conducció sobre el pendent subumbral, el corrent i la reducció de la barrera induïda per drenador (DIBL). A més, es demostra i explica la fusió de dos efectes relacionats amb el pendent subumbral i el DIBL. La validesa del concepte de dimensions DG equivalents es demostra mitjançant el mesurament i les dades de simulació de TCAD Sentaurus, mentre que el mètode de wavelets es verifica mitjançant simulacions NanoMOS NEGF.Las geometrías de transistores de hoy están en el rango de nanómetros de un solo dígito. En consecuencia, las funcionalidades de los dispositivos se ven afectadas negativamente por los efectos de canal corto y de mecánica cuántica (SCE y QMEs). Una transición de la geometría del transistor de efecto de campo de tipo FinFET a Gate-All -Around (GAA) FETs tales como FETs de nanohilos cilíndricos (NW) y de nanoplacas de silicio (SiNS) se prevén en los próximos nodos tecnológicos para suprimir los SCE y garantizar una mayor miniaturización del MOSFET. Esta disertación se centra en el modelado analítico de FETs de tipo NW y SiNS de canal ultracorto. Se introduce un concepto de dimensiones de doble puerta (DG) equivalente para transferir un modelo de potencial de DG analítico a FET de NW. Un modelo de corriente de DG compacto se modifica aprovechando la simetría rotacional de los FET de NW. El efecto del confinamiento cuántico (QC) es implementado considerando el ensanchamiento adicional de la banda prohibida en el cálculo de una concentración de portadores de carga intrínseca efectiva y en el cálculo del voltaje de umbral. El efecto de corriente túnel directa de fuente a drenador (DSDT) en SiNS FET ultraescalados se modela con el nuevo método de wavelets. Este modelo calcula analíticamente la probabilidad de tunelización para cada energía del electrón aproximando la forma de la barrera de potencial mediante una barrera rectangular con una altura de barrera equivalente. Usando la fórmula de corriente túnel de Tsu-Esaki no analíticamente integrable, se presenta un método analítico denominado modelo cuasi-compacto (QCM), querequiere una iteración de Newton y una interpolación lineal de la densidad de corriente de efecto túnel. Además, se realiza un análisis criogénico en temperatura y dopaje. Se investiga la fuerte influencia del nivel de Fermi de la fuente la sobre la pendiente subumbral, la corriente y la reducción del efecto DIBL. Además, se demuestra y explica la fusión de dos efectos relacionados con la pendiente subumbral y el DIBL. La validez del concepto de dimensiones DG equivalentes se demuestra mediante datos de mediciones y de simulaciones TCAD Sentaurus, mientras que el método de wavelets se verifica mediante simulaciones NanoMOS NEGF.Today's transistor geometries are in the single-digit nanometer range. Consequently, device functionalities are negatively affected by short-channel and quantum mechanical effects (SCEs & QMEs). A transition from fin field-effect transistor (FinFET) geometry to gate-all-around (GAA) FETs such as cylindrical nanowire (NW) and silicon nanosheet (SiNS) FETs is envisioned in the upcoming technology nodes to suppress SCEs and ensure further MOSFET miniaturization. This dissertation focuses on the analytical modeling of ultrashort-channel NW and SiNS FETs. An equivalent double-gate (DG) dimensions concept is introduced to transfer an analytical DG potential model to NW FETs. A compact DG current model is modified by exploiting the rotational symmetry of NW FETs. The effect of quantum confinement (QC) is implemented by considering the additional bandgap widening in the calculation of an effective intrinsic charge carrier concentration and in the calculation of the threshold voltage. The effect of direct source-to-drain tunneling (DSDT) current in ultrascaled SiNS FETs is modeled with the new wavelet approach. This model calculates the tunneling probability analytically for each electron energy by approximating the potential barrier shape by a rectangular barrier with an equivalent barrier height. Due to the nonanalytically integrable Tsu-Esaki tunneling formula an analytical approach named quasi-compact model (QCM) is presented. This approach requires, among other approximations, a Newton iteration, and a linear interpolation of the tunneling current density. Furthermore, a cryogenic temperature and doping analysis is performed. The strong influence of the distance of the source related Fermi level from the conduction band edge on the subthreshold swing, current, and drain-induced barrier lowering (DIBL) saturation is investigated. Also, the merging of two subthreshold swing and DIBL effects is demonstrated and explained. The validity of the equivalent DG dimensions concept is proven by measurement and TCAD Sentaurus simulation data, while the wavelet approach is verified by NanoMOS NEGF simulations

Vertical III-V Nanowire Transistors for Low-Power Electronics

Power dissipation has been the major challenge in the downscaling of transistor technology. Metal-Oxide-Semiconductor Field-Effect Transistors (MOSFETs) have struggled to keep a low power consumption while still maintaining a high performance due to the low carrier mobilities of Si but also due to their inherent minimum inverse subthreshold slope (S ≥ 60 mV/dec) which is limited by thermionic emission. This thesis work studied the capabilities and limitations of III-V based vertical nanowire n-type Tunneling Field-Effect Transistor (TFET) and p-type MOSFET (PMOS). InAs/InGaAsSb/GaSb heterojunction was employed in the whole study. The main focus was to understand the influence of the device fabrication processes and the structural factors of the nanowires such as band alignment, composition and doping on the electrical performance of the TFET. Optimizations of the device processes including spacer technology improvement, Equivalent Oxide Thickness (EOT) downscaling, and gate underlap/overlap were explored utilizing structural characterizations. Systematic fine tuning of the band alignment of the tunnel junction resultedin achieving the best performing sub-40 mV/dec TFETs with S = 32 mV/decand ION = 4μA/μm for IOFF = 1 nA/μm at VDS = 0.3 V. The suitability of employing TFET for electronic applications at cryogenic temperatures has been explored utilizing experimental device data. The impact of the choice of heterostructure and dopant incorporation were investigated to identify the optimum operating temperature and voltage in different temperature regimes. A novel gate last process self-aligning the gate and drain contacts to the intrinsic and doped segments, respectively was developed for vertical InGaAsSb-GaAsSb core-shell nanowire transistors leading to the first sub-100 mV/dec PMOS with S = 75 mV/dec, significant ION/ IOFF = 104 and IMIN < 1 nA/μm at VDS = -0.5 V

Vertical III-V Nanowire Tunnel Field-Effect Transistor

In this thesis fabrication and optimization of vertical III-V Tunneling Field-Effect transistors was explored. Usage of vertical nanowires, allows for combination of materials with large lattice mismatch in the same nanowire structure. TFETs in this thesis were fabricated using vertical InAs/GaSb or InAs/InGaAsSb/GaSb nanowires of high material quality. Usage of these material systems allowed for fabrication of devices with staggered and broken band-gap alignment. To fully harvest the benefits from these structures, the fabrication process was optimized. This was performed by exploring different spacer and gate technologies, required for vertical devices. Furthermore, improvement of electrostatics was achieved by reduction of the channel diameter and high-κ interface. Further improvements of the performance were achieved by scaling of the device dimensions such as nanowire lengths, spacer thickness, and gate-length. Used fabrication techniques allowed us to fabricate devices with a channel diameter of 11 nm. By switching from InAs/GaSb to InAs/InGaAsSb/GaSb allowed for optimization of the heterojunction, which allowed us to fabricate devices with record performance, reaching a minimum subthreshold swing of 48 mV/decade and a record high I60 of 0.31 μA/μm at a drive voltage of 0.3 V. Stability of the process allowed us to demonstrate data from a large number of TFETs with ability to operate below the thermal limit of 60 mV/decade. This allowed us to study correlations between important device parameter such as: I60, on-current, subthreshold swing, and off-current. Using transmission electron microscopy, the heterojunction was characterized. Furthermore, TCAD modeling was performed to understand what limits the performance of these devices. Also, electrical measurement of the random telegraph noise allowed us to understand the impact the oxide defects have on highly scaled devices

Vertical III-V Nanowire Transistors for Low-Power Logic and Reconfigurable Applications

With rapid increase in energy consumption of electronics used in our daily life, the building blocks — transistors — need to work in a way that has high energy efficiency and functional density to meet the demand of further scaling. III-V channel combined with vertical nanowire gate-all-around (GAA) device architecture is a promising alternative to conventional Si transistors due to its excellent electrical properties in the channel and electrostatic control across the gate oxide in addition to reduced footprint. Based on this platform, two major objectives of this thesis are included: 1) to improve the performance of III-V p-type metal-oxide-semiconductor field-effect transistors (MOSFETs) and tunnel FETs (TFETs) for low-power digital applications; 2) to integrate HfO2-based ferroelectric gate onto III-V FETs (FeFETs) and TFETs (ferro-TFETs) to enable reconfigurable operation for high functional density.The key bottleneck for all-III-V CMOS is its p-type MOSFETs (p-FETs) which are mainly made of GaSb or InGaSb. Rich surface states of III-Sb materials not only lead to decreased effective channel mobility due to more scattering, but also deteriorate the electrostatics. In this thesis, several approaches to improve p-FET performance have been explored. One strategy is to enhance the hole mobility by introducing compressive strain into III-Sb channel. For the first time, a high and uniform compressive strain near 1% along the transport direction has been achieved in downscaled GaSb nanowires by growing and engineering GaSb-GaAsSb core-shell structure, aiming for potential hole mobility enhancement. In addition, surface passivation using digital etch has been developed to improve the electrostatics with subthreshold swing (SS) down to 107 mV/dec. Moreover, the on-state performance including on-current (Ion) and transconductance (gm) have been enhanced by ∼50% using annealing with H2-based forming gas. Lastly, a novel p-FET structure with (In)GaAsSb channel has been developed and further improved off-state performance with SS = 71 mV/dec, which is the lowest value among all reported III-V p-FETs.Despite subthermionic operation, TFETs usually suffer from low drive current as well as the current operating below 60 mV/dec (I60). The second focus of this thesis is to fine-tune the InAs/(In)GaAsSb heterostructure tunnel junction and the doping in the source segment during epitaxy. As a result, a substantially increased I60 (>1 µA/µm) and Ion up to 40 µA/µm at source-drain bias of 0.5 V have been achieved, reaching a record compared to other reported TFETs.Finally, emerging ferroelectric oxide based on Zr-doped HfO2 (HZO) has been successfully integrated onto III-V vertical nanowire transistors to form FeFETs and ferro-TFETs with GAA architecture. The corresponding electrical performance and reliability have been carefully characterized with both DC and pulsed I-V measurements. The unique band-to-band tunneling in InAs/(In)GaAsSb/GaSb heterostructure TFET creates an ultrashort effective channel, leading to detection of localized potential variation induced by single domains and defects in nanoscale ferroelectric HZO without physical gate-length scaling. By introducing gate/source overlap structure in the ferro-TFET, non-volatile reconfigurable signal modulation with multiple modes including signal transmission, phase shift, frequency doubling, and mixing has been achieved in a single device with low drive voltage and only ∼0.01 µm2 footprint, thus increasing both functional density andenergy efficiency

Fabrication and characterization of III-V tunnel field-effect transistors for low voltage logic applications

With voltage scaling to reduce power consumption in scaled transistors the subthreshold swing is becoming a critical factor influencing the minimum voltage margin between the transistor on and off-states. Conventional metal-oxide-semiconductor field-effect transistors (MOSFETs) are fundamentally limited to a 60 mV/dec swing due to the thermionic emission current transport mechanism at room temperature. Tunnel field-effect transistors (TFETs) utilize band-to-band tunneling as the current transport mechanism resulting in the potential for sub-60 mV/dec subthreshold swings and have been identified as a possible replacement to the MOSFET for low-voltage logic applications. The TFET operates as a gated p-i-n diode under reverse bias where the gate electrode is placed over the intrinsic channel allowing for modulation of the tunnel barrier thickness. When the barrier is sufficiently thin the tunneling probability increases enough to allow for significant number of electrons to tunnel from the source into the channel. To date, experimental TFET reports using III-V semiconductors have failed to produce devices that combine a steep subthreshold swing with a large enough drive current to compete with scaled CMOS. This study developed the foundations for TFET fabrication by improving an established Esaki tunnel diode process flow and extending it to include the addition of a gate electrode to form a TFET. The gating process was developed using an In0.53Ga0.57As TFET which demonstrated a minimum subthreshold slope of 100 mV/dec. To address the issue of TFET drive current an InAs/GaSb heterojunction TFET structure was investigated taking advantage of the smaller tunnel barrier height

Substrate Effects And Dielectric Integration In 2d Electronics

The ultra-thin body of monolayer (and few-layer) two dimensional (2D) semiconducting materials such as transitional metal dichalconiges (TMDs), black phosphorous (BP) has demonstrated tremendous beneficial physical, transport, and optical properties for a wide range of applications. Because of their ultrathin bodies, the properties of 2D materials are highly sensitive to environmental effects. Particularly, the performance of 2D semiconductor electronic devices is strongly dependent on the substrate/dielectric properties, extrinsic impurities and absorbates. In this work, we systematically studied the transport properties of mechanically exfoliated few layer TMD field-effect transistors (FETs) consistently fabricated on various substrates including SiO2,Parylene –C, Al2O3, SiO2 modified by octadecyltrimethoxysilane (OTMS) self-assembled monolayer (SAMs), and hexagonal boron nitride (h-BN). We performed variable temperature transport measurements to understand the effects of various scattering mechanisms such as remote surface phonon scattering, coulomb scattering, surface roughness scattering on the mobility of these devices. To reveal the intrinsic channel properties, we also investigated TMD devices encapsulated by h-BN. To further optimize the dielectric interface and electrostatic control of the TMD channels, we developed a novel thermal-oxidation method to turn few-layer 2D metals into ultrathin and atomically flat high –κ dielectrics. In order to optimize the performance of TMD electronic devices, it is also critical to fabricate low resistance ohmic contacts required for effectively injecting charge carriers into the TMD channel. Along this direction, we developed a new contact strategy to minimize the contact resistance for a variety of TMDs by van der Waals assembly of doped TMDs as contacts and undoped TMDs as channel materials. The developed unique method for low-resistance ohmic contacts achieved using the 2D/2D contact strategy and novel technique for high-k dielectric integration is expected to open the path to explore the rich quantum physics in TMDs 2DEGs and 2DHGs

Optimization Of Transition-Metal Dichalcogenides Based Field- Effect- Transistors Via Contact Engineering

ABSTRACT Optimization of Transition-Metal Dichalcogenides based Field- Effect-Transistors via contact engineering by Meeghage M Perera September , 2016 Advisor : Dr. Zhixian Zhou Major: Physics (Condensed mater physics/nano-electronics) Degree: Doctor of Philosophy Layered transition Metal Dichalcogenides (TMDs) have demonstrated a wide range of remarkable properties for applications in next generation nano-electronics. These systems have displayed many “graphene-like” properties including a relatively high carrier mobility, mechanical flexibility, chemical and thermal stability, and moreover offer the significant advantage of a substantial band gap. However, the fabrication of high performance field-effect transistors (FETs) of TMDs is challenging mainly due to the formation of a significant Schottky barrier at metal/TMD interface in most cases. The main goal of this study is to develop novel contact engineering strategies to achieve low-resistance Ohmic contacts. Our first approach is to use Ionic Liquid (IL) gating of metal contacted MoS2 FETs to achieve highly transparent tunneling contacts due to the strong band banding at metal/MoS2 interface. The substantially reduced contact resistance in ionic-liquid-gated bilayer and few-layer MoS2 FETs results in an ambipolar behavior with high ON/OFF ratios, a near-ideal subthreshold swing, and significantly improved field-effect mobility. Remarkably, the mobility of a 3-nm-thick MoS2 FET with an IL gate was found to increase from ~ 100 cm2V-1s-1 to ~ 220 cm2V-1s-1 as the temperature decreased from 180 K to 77 K. This finding is in quantitative agreement with the true channel mobility measured by four-terminal measurement, suggesting that the mobility is predominantly limited by phonon-scattering. To further improve the contacts of TMD devices, graphene was used as work function tunable electrodes. In order to achieve low Schottky barrier height, both IL gating and surface charge transfer doping were used to tune the work function of graphene electrodes close to the conduction band edge of MoS2. As a result, the performance of our graphene contacted MoS2 FETs is limited by the channel rather than contacts, which is further verified by four-terminal measurements. Finally, degenerately doped TMDs are used as drain/source electrodes to form 2D/2D van der Waals contacts, which are air and thermally stable. WSe2 devices with 2D/2D contacts and 0.01% Nb doped WSe2channel show a high ON/OFF ratio and high field-effect mobility of 175 cm2V-1S-1 at room temperature, which increases to 654 cm2V-1S-1 at cryogenic temperatures. As the doping concentration increases, both the ON/OFF ratio and mobility decrease. These contact engineering strategies overcome a major challenge in the development of electronics based on 2D materials beyond graphene

Doped And Chemically Transformed Transition Metal Dichalcogenides (tmdcs) For Two-Dimensional (2d) Electronics

Transition metal dichalcogenides (TMDCs) as the semiconductor counterparts of gra-phene have emerged as promising channel materials for flexible electronic and optoelectronic devices. The 2D layer structure of TMDCs enables the ultimate scaling of TMDC-based devices down to atomic thickness. Furthermore, the absence of dangling bonds in these materials helps to form high quality heterostructures with ultra-clean interfaces. The main objective of this work is to develop novel approaches to fabricating TMDC-based 2D electronic devices such as diodes and transistors. In the first part, we have fabricated 2D p-n junction diodes through van der Waals assembly of heavily p-doped MoS2 (WSe2) and lightly n-doped MoS2 to form vertical homo-(hetero-) junctions, which allows to continuously tune the electron concentration on the n-side for a wide range. In sharp contrast to conventional p-n junction diodes, we have observed nearly exponential dependence of the reverse-current on gate-voltage in our 2D p-n junction devices, which can be attributed to band-to-band tunneling through a gate-tunable tunneling barrier. In the second part, we developed a new strategy to engineer high-κ dielectrics by con-verting atomically thin metallic 2D TMDCs into high-κ dielectrics because it remains a signifi-cant challenge to deposit uniform high-κ dielectric thin films on TMDCs with ALD due to the lack of dangling bonds on the surfaces of TMDCs. In our study, we converted mechanically ex-foliated atomically thin layers of a 2D metal, TaS2 (HfSe2) into a high-κ dielectric, Ta2O5 (HfO2) by thermal oxidation. X-ray photoelectron spectroscopy (XPS), transmission electron microscopy (TEM), energy dispersive spectroscopy (EDS), and atomic force microscopy (AFM) were used to understand the phase conversion process. Capacitance-voltage (C-V) measure-ments were carried out to determine the dielectric constant of thermally oxidized dielec-trics. We fabricated MoS2 field-effect transistors (FETs) with thermally oxidized ultra-thin and ultra-smooth Ta2O5 as top-gate and bottom-gate high-κ dielectric layers. We observed promis-ing device performance, including a nearly ideal subthreshold swing of ~ 61 mV/dec at room temperature, negligible hysteresis, drain-current saturation in the output characteristics, a high on/off ratio ~ 106, and a room temperature field-effect mobility exceeding 60 cm2/Vs. To fur-ther reduce the leak current and improve the device performance, we have also investigated the chemical transformation of HfSe2 to HfO2 high-κ dielectric, which has significantly larger band gap than Ta2O5

Realisation of III-V Tunnel-FET with in-situ ultimate scaled gate stack for high performance power efficient CMOS

The main objective of this thesis is realising a non-planar III-V Tunnel-FET for low power device applications. The differentiating aspect of this work is based around clustered inductively coupled plasma (ICP) etch and atomic layer deposition (ALD) tools. This approach was intended to mitigate native oxide formation on etched III-V surfaces prior to gate stack deposition by ALD. The use of a cluster tool also offers the benefit of cleaning III-V surfaces “in-situ” using low damage plasma based approaches. In addition, activity on scaling the equivalent oxide thickness of the gate stack and evaluating different heterostructures are explored in this work for the realisation of high performance TunnelFET. Initially, gate stacks on both p- and n- (110)-oriented In0.53Ga0.47As were examined to understand the basic electrical properties of these interfaces, important for non-planar device architectures. An optimised process, based on ex-situ sulphur-based passivation before ALD of gate dielectrics, and forming gas annealing (FGA) after gate metal deposition, is demonstrated for the first time to show significant Fermi level movement through the bandgap. Quantitatively, interface state density (Dit) values in the range of 0.87-1.8 × 1012 cm-2eV-1 around the midgap energy level were obtained. The lowest Dit value is estimated to be 3.1 × 1012 cm-2eV-1 close to the conduction band edge showing the combination of sulphur passivation and (FGA) is effective is passivating the trap states in the upper half of the bandgap on Al2O3/In0.53Ga0.47As (110) MOSCAPs. Furthermore, by analysis of CV hysteresis biasing at 1.1 V beyond the flatband voltage, the border trap density on n-type MOSCAPs was observed to reduce, after FGA from 1.8 × 1012 cm-2 to 5.3 × 1011 cm-2. The result observed in p-type MOSCAPs is in contrast, with increasing border trap density from 7.3 × 1011 cm-2 to 1.4 × 1012 cm-2 under the similar bias condition, i.e. the FGA process is not as effective in passivating states close to the valence band. In addition, the analysis undertaken in this thesis determined the value of the conduction band offset at the Al2O3/In0.53Ga0.47As (110) to be is 1.81eV – the first report of this parameter. The non-planar devices of this work also require low damage etching processes for fin/wire formation. Therefore, the performance of in-situ deposited gate stacks to In0.53Ga0.47As (100)- and (110)-oriented substrates which had been subjected to a CH4/Cl2/H2 based ICP etch chemistry, which forms vertical InGaAs sidewall profiles, were assessed. Based on CV and IV, and X-ray Photo-Spectroscopy (XPS) spectral analyses, the performance of gate stacks deposited on (110)-oriented In0.53Ga0.47As subjected to a ICP dry etch suffers more damage compared to gate stacks on (100)-oriented In0.53Ga0.47As. To minimise the etching damage, cyclic TMA/plasma gas pretreatment prior to ALD is introduced on both (100)- and (110)-oriented surfaces. The interface trap density of gate stacks on (110)-oriented In0.53Ga0.47As with TMA/H2 gas pre-treatment improves from 6 × 1011 cm-2eV-1 to 2.8 × 1011 cm-2eV-1 close to the conduction band edge. Based on this in-situ gate stack process, a gate stack with reduced capacitor equivalent thickness (CET) on both (100) and (110) oriented surfaces are achieved by using a TiN layer deposited in-situ by ALD before ex-situ gate metal deposition. The lowest CET was around 1.09 nm for a HfO2/TiN stack deposited on (100)-oriented In0.53Ga0.47As. This optimised gate stack was included in an InGaAs-based tunnel-FET process flow using p-n, p-i-n, and p-n-i-n heterostructures. Comparing with p-n Tunnel-FETs, the pi-n structure provides better electrical characteristics for In0.53Ga0.47As with a subthreshold swing (SS) of 120 mV/dec at the condition of VDS = 0.05V. The peak transconductance peak of the p-i-n Tunnel-FET at the condition of VDS = 0.3V is around 6 uS/um. Next, an inserted n-pocket p-n-i-n Tunnel-FET was studied. In addition to providing comparable on current with the p-i-n Tunnel-FET of 1.1 uA/um at the bias condition of VDS = 300mV, the subthreshold swing of the p-n-i-n devices improves by 46% due to the lower leakage floor from the n-pocket layer incorporation. Most importantly, the non-planar configuration of the p-n-i-n Tunnel-FET improves both the SS and on-current to 152 mV/dec at the bias condition of VDS = 300mV and 1.3 uA/um at the bias condition of VDS = 500mV and VGS = 900mV, respectively. Above these aspects and benchmark, all this data implies that a non-planar p-n-i-n InGaAs TunnelFET is a promising candidate for future generations of low power applications

Design, Modeling and Analysis of Non-classical Field Effect Transistors

Transistor scaling following per Moore\u27s Law slows down its pace when entering into nanometer regime where short channel effects (SCEs), including threshold voltage fluctuation, increased leakage current and mobility degradation, become pronounced in the traditional planar silicon MOSFET. In addition, as the demand of diversified functionalities rises, conventional silicon technologies cannot satisfy all non-digital applications requirements because of restrictions that stem from the fundamental material properties. Therefore, novel device materials and structures are desirable to fuel further evolution of semiconductor technologies. In this dissertation, I have proposed innovative device structures and addressed design considerations of those non-classical field effect transistors for digital, analog/RF and power applications with projected benefits. Considering device process difficulties and the dramatic fabrication cost, application-oriented device design and optimization are performed through device physics analysis and TCAD modeling methodology to develop design guidelines utilizing transistor\u27s improved characteristics toward application-specific circuit performance enhancement. Results support proposed device design methodologies that will allow development of novel transistors capable of overcoming limitation of planar nanoscale MOSFETs. In this work, both silicon and III-V compound devices are designed, optimized and characterized for digital and non-digital applications through calibrated 2-D and 3-D TCAD simulation. For digital functionalities, silicon and InGaAs MOSFETs have been investigated. Optimized 3-D silicon-on-insulator (SOI) and body-on-insulator (BOI) FinFETs are simulated to demonstrate their impact on the performance of volatile memory SRAM module with consideration of self-heating effects. Comprehensive simulation results suggest that the current drivability degradation due to increased device temperature is modest for both devices and corresponding digital circuits. However, SOI FinFET is recommended for the design of low voltage operation digital modules because of its faster AC response and better SCEs management than the BOI structure. The FinFET concept is also applied to the non-volatile memory cell at 22 nm technology node for low voltage operation with suppressed SCEs. In addition to the silicon technology, our TCAD estimation based on upper projections show that the InGaAs FinFET, with superior mobility and improved interface conditions, achieve tremendous drive current boost and aggressively suppressed SCEs and thereby a strong contender for low-power high-performance applications over the silicon counterpart. For non-digital functionalities, multi-fin FETs and GaN HEMT have been studied. Mixed-mode simulations along with developed optimization guidelines establish the realistic application potential of underlap design of silicon multi-Fin FETs for analog/RF operation. The device with underlap design shows compromised current drivability but improve analog intrinsic gain and high frequency performance. To investigate the potential of the novel N-polar GaN material, for the first time, I have provided calibrated TCAD modeling of E-mode N-polar GaN single-channel HEMT. In this work, I have also proposed a novel E-mode dual-channel hybrid MIS-HEMT showing greatly enhanced current carrying capability. The impact of GaN layer scaling has been investigated through extensive TCAD simulations and demonstrated techniques for device optimization