Full Duplex CMOS Transceiver with On-Chip Self-Interference Cancelation

abstract: The demand for the higher data rate in the wireless telecommunication is increasing rapidly. Providing higher data rate in cellular telecommunication systems is limited because of the limited physical resources such as telecommunication frequency channels. Besides, interference with the other users and self-interference signal in the receiver are the other challenges in increasing the bandwidth of the wireless telecommunication system. Full duplex wireless communication transmits and receives at the same time and the same frequency which was assumed impossible in the conventional wireless communication systems. Full duplex wireless communication, compared to the conventional wireless communication, doubles the channel efficiency and bandwidth. In addition, full duplex wireless communication system simplifies the reusing of the radio resources in small cells to eliminate the backhaul problem and simplifies the management of the spectrum. Finally, the full duplex telecommunication system reduces the costs of future wireless communication systems. The main challenge in the full duplex wireless is the self-interference signal at the receiver which is very large compared to the receiver noise floor and it degrades the receiver performance significantly. In this dissertation, different techniques for the antenna interface and self-interference cancellation are proposed for the wireless full duplex transceiver. These techniques are designed and implemented on CMOS technology. The measurement results show that the full duplex wireless is possible for the short range and cellular wireless communication systems.Dissertation/ThesisDoctoral Dissertation Engineering 201

Design of Energy-Efficient A/D Converters with Partial Embedded Equalization for High-Speed Wireline Receiver Applications

As the data rates of wireline communication links increases, channel impairments such as skin effect, dielectric loss, fiber dispersion, reflections and cross-talk become more pronounced. This warrants more interest in analog-to-digital converter (ADC)-based serial link receivers, as they allow for more complex and flexible back-end digital signal processing (DSP) relative to binary or mixed-signal receivers. Utilizing this back-end DSP allows for complex digital equalization and more bandwidth-efficient modulation schemes, while also displaying reduced process/voltage/temperature (PVT) sensitivity. Furthermore, these architectures offer straightforward design translation and can directly leverage the area and power scaling offered by new CMOS technology nodes. However, the power consumption of the ADC front-end and subsequent digital signal processing is a major issue. Embedding partial equalization inside the front-end ADC can potentially result in lowering the complexity of back-end DSP and/or decreasing the ADC resolution requirement, which results in a more energy-effcient receiver. This dissertation presents efficient implementations for multi-GS/s time-interleaved ADCs with partial embedded equalization. First prototype details a 6b 1.6GS/s ADC with a novel embedded redundant-cycle 1-tap DFE structure in 90nm CMOS. The other two prototypes explain more complex 6b 10GS/s ADCs with efficiently embedded feed-forward equalization (FFE) and decision feedback equalization (DFE) in 65nm CMOS. Leveraging a time-interleaved successive approximation ADC architecture, new structures for embedded DFE and FFE are proposed with low power/area overhead. Measurement results over FR4 channels verify the effectiveness of proposed embedded equalization schemes. The comparison of fabricated prototypes against state-of-the-art general-purpose ADCs at similar speed/resolution range shows comparable performances, while the proposed architectures include embedded equalization as well

Performance Analysis of Discrete Wavelet Multitone Transceiver for Narrowband PLC in Smart Grid

Smart Grid is an abstract idea, which involves the utilization of powerlines for sensing, measurement, control and communication for efficient utilization and distribution of energy, as well as automation of meter reading, load management and capillary control of Green Energy resources connected to the grid. Powerline Communication (PLC) has assumed a new role in the Smart Grid scenario, adopting the narrowband PLC (NB-PLC) for a low cost and low data rate communication for applications such as, automatic meter reading, dynamic management of load, etc. In this paper, we have proposed and simulated a discrete wavelet multitone (DWMT) transceiver in the presence of impulse noise for the NB-PLC channel applications in Smart Grid. The simulation results show that a DWMT transceiver outperforms a DFT-DMT with reference to the bit error rate (BER) performance

Design of Low-Power NRZ/PAM-4 Wireline Transmitters

Rapid growing demand for instant multimedia access in a myriad of digital devices has pushed the need for higher bandwidth in modern communication hardwares ranging from short-reach (SR) memory/storage interfaces to long-reach (LR) data center Ethernets. At the same time, comprehensive design optimization of link system that meets the energy-efficiency is required for mobile computing and low operational cost at datacenters. This doctoral study consists of design of two low-swing wireline transmitters featuring a low-power clock distribution and 2-tap equalization in energy-efficient manners up to 20-Gb/s operation. In spite of the reduced signaling power in the voltage-mode (VM) transmit driver, the presence of the segment selection logic still diminishes the power saving benefit. The first work presents a scalable VM transmitter which offers low static power dissipation and adopts an impedance-modulated 2-tap equalizer with analog tap control, thereby obviating driver segmentation and reducing pre-driver complexity and dynamic power. Per-channel quadrature clock generation with injection-locked oscillators (ILO) allows the generation of rail-to-rail quadrature clocks. Energy efficiency is further improved with capacitively driven low-swing global clock distribution and supply scaling at lower data rates, while output eye quality is maintained at low voltages with automatic phase calibration of the local ILO-generated quarter-rate clocks. A prototype fabricated in a general purpose 65 nm CMOS process includes a 2 mm global clock distribution network and two transmitters that support an output swing range of 100-300mV with up to 12-dB of equalization. The transmitters achieve 8-16 Gb/s operation at 0.65-1.05 pJ/b energy efficiency. The second work involves a dual-mode NRZ/PAM-4 differential low-swing voltage-mode (VM) transmitter. The pulse-selected output multiplexing allows reduction of power supply and deterministic jitter caused by large on-chip parasitic inherent in the transmission-gate-based multiplexers in the earlier work. Analog impedance control replica circuits running in the background produce gate-biasing voltages that control the peaking ratio for 2-tap feed-forward equalization and PAM-4 symbol levels for high-linearity. This analog control also allows for efficient generation of the middle levels in PAM-4 operation with good linearity quantified by level separation mismatch ratio of 95%. In NRZ mode, 2-tap feedforward equalization is configurable in high-performance controlled-impedance or energy-efficient impedance-modulated settings to provide performance scalability. Analytic design consideration on dynamic power, data-rate, mismatch, and output swing brings optimal performance metric on the given technology node. The proof-of-concept prototype is verified on silicon with 65 nm CMOS process with improved performance in speed and energy-efficiency owing to double-stack NMOS transistors in the output stage. The transmitter consumes as low as 29.6mW in 20-Gb/s NRZ and 25.5mW in the 28-Gb/s PAM-4 operations

A 90 nm CMOS 16 Gb/s Transceiver for Optical Interconnects

Interconnect architectures which leverage high-bandwidth optical channels offer a promising solution to address the increasing chip-to-chip I/O bandwidth demands. This paper describes a dense, high-speed, and low-power CMOS optical interconnect transceiver architecture. Vertical-cavity surface-emitting laser (VCSEL) data rate is extended for a given average current and corresponding reliability level with a four-tap current summing FIR transmitter. A low-voltage integrating and double-sampling optical receiver front-end provides adequate sensitivity in a power efficient manner by avoiding linear high-gain elements common in conventional transimpedance-amplifier (TIA) receivers. Clock recovery is performed with a dual-loop architecture which employs baud-rate phase detection and feedback interpolation to achieve reduced power consumption, while high-precision phase spacing is ensured at both the transmitter and receiver through adjustable delay clock buffers. A prototype chip fabricated in 1 V 90 nm CMOS achieves 16 Gb/s operation while consuming 129 mW and occupying 0.105 mm^2

Wideband receive spatial modulation with time domain pre-equalizer for large MIMO systems

© 2018 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes,creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other worksReceive spatial modulation (RSM) schemes are promising for massive multiple-input-multiple-output (MIMO) systems at millimeter wave (mmWave) bands because they require reduced complexity and low consumption hardware at the user terminal and exploit the receive spatial dimension to attain high spectral efficiency. To the best of our knowledge, these schemes have been developed for narrowband transmission. In this paper, we adapt RSM schemes for outdoor wideband mmWave massive MIMO systems. We consider the downlink of a single user system operating with single carrier RSM and design a low complexity time-domain finite impulse response pre-equalizer to combat the intersymbol interference caused by the wideband transmission, assuming imperfect channel knowledge. We show that receive antenna selection (RAS) is necessary for attaining high spectral efficiency and we suggest fast and efficient RAS algorithm. Simulation results show that the proposed RSM scheme achieves comparable spectral efficiency to the fully digital orthogonal frequency division multiplexing MIMO system with superior energy efficiency.Peer ReviewedPostprint (author's final draft

Broadband Receiver Electronic Circuits for Fiber-Optical Communication Systems

The exponential growth of internet traffic drives datacenters to constantly improve their capacity. As the copper based network infrastructure is being replaced by fiber-optical interconnects, new industrial standards for higher datarates are required. Several research and industrial organizations are aiming towards 400 Gb Ethernet and beyond, which brings new challenges to the field of high-speed broadband electronic circuit design. Replacing OOK with higher M-ary modulation formats and using higher datarates increases network capacity but at the cost of power. With datacenters rapidly becoming significant energy consumers on the global scale, the energy efficiency of the optical interconnect transceivers takes a primary role in the development of novel systems. There are several additional challenges unique in the design of a broadband shortreach fiber-optical receiver system. The sensitivity of the receiver depends on the noise performance of the PD and the electronics. The overall system noise must be optimized for the specific application, modulation scheme, PD and VCSEL characteristics. The topology of the transimpedance amplifier affects the noise and frequency response of the PD, so the system must be optimized as a whole. Most state-of-the-art receivers are built on high-end semiconductor SiGe and InP technologies. However, there are still several design decisions to be made in order to get low noise, high energy efficiency and adequate bandwidth. In order to overcome the frequency limitations of the optoelectronic components, bandwidth enhancement and channel equalization techniques are used. In this work several different blocks of a receiver system are designed and characterized. A broadband, 50 GHz bandwidth CB-based TIA and a tunable gain equalizer are designed in a 130 nm SiGe BiCMOS process. An ultra-broadband traveling wave amplifier is presented, based on a 250 nm InP DHBT technology demonstrating a 207 GHz bandwidth. Two TIA front-end topologies with 133 GHz bandwidth, a CB and a CE with shunt-shunt feedback, based on a 130 nm InP DHBT technology are designed and compared

Behavioral modelling of GaN RF-power amplifier

Abstract. In this thesis memory effects and nonlinearities of Gallium Nitride (GaN) Doherty power amplifier (PA) were studied for measurement based behavioral modelling purposes. In SoC simulations a PA model is needed to simulate the performance of different linearization algorithms and to optimize the digital pre-distortion (DPD) design to cancel the memory effects of the PA, thus the model needs to be capable of modelling the memory effects sufficiently. Aim was to study if there were any differences in power amplifiers behavior and memory effects between time division duplexing (TDD) and frequency division duplexing (FDD) and what kind of model topologies are needed to model the PA sufficiently. In this thesis, two PAs were measured in different operation modes. Characterization setup was built, and an equalizer was characterized to remove the frequency selectivity of the test setup to obtain more accurate measurement results. Two signal bandwidths of 20MHz and 100MHz were used to extract data from power amplifier output with FDD and TDD operation. A generalized memory polynomial was fitted to model the PAs and found to be sufficient to model FDD operation. However, with TDD operation generalized memory polynomial model was not as accurate due to complex memory effects such as thermal and trapping memory. Models were also validated by using a digital pre-distorter and compared with measurement results and the models seem to work well and provide adjacent channel power ratio (ACPR) of -53.5dBc on lower channel and -53.3dBc on upper channel with 100MHz signal.GaN RF-tehovahvistimen käyttäytymistason mallinnus. Tiivistelmä. Tässä työssä tutkittiin Galliumnitraatti (GaN) Doherty-tehovahvistimen (PA) muistiilmiöitä ja epälineaarisuutta mittauksiin perustuvaa käyttäytymistason mallinnusta varten. SoC-simuloinneissa tarvitaan PA-mallia erilaisten linearisointialgoritmien suorituskyvyn simuloimiseksi. Erityisesti digitaalisen esisäröttimen (DPD) suunnittelun optimoimiseksi tehovahvistimessa esiintyvän muistin kumoamiseksi mallin on pystyttävä mallintamaan muistia riittävällä tarkkuudella. Työn tavoitteena oli selvittää, onko tehovahvistimien käyttäytymisessä ja muisti-ilmiöissä eroja aika- ja taajuusdupleksoinnin (TDD, FDD) välillä ja millaisia mallitopologioita tarvitaan, jotta tehovahvistinta voidaan mallintaa riittävällä tarkkuudella. Tässä työssä käytettiin kahta tehovahvistinta eri toimintatilojen mittaamiseen. Työssä rakennettiin mittausympäristö ja lisättiin taajuuskorjain kumoamaan mittausympäristön taajuusselektiivisyyttä. Kahta signaalinkaistanleveyttä 20 MHz:a ja 100 MHz:ä käytettiin datan keräämiseen tehovahvistimen ulostulosta aika- ja taajusjakoista dupleksointia käyttäen. Tehovahvistimen mallintamiseen sovitettiin muistipolynomi, jonka todettiin olevan riittävän tarkka FDD-toiminnan mallintamiseen, mutta TDD-toiminnassa malli ei ollut yhtä tarkka monimutkaisten muisti-ilmiöiden, kuten lämpö- ja elektronien ansoitusmuistin, vuoksi. Mallit validoitiin myös käyttämällä digitaalista esisärötystä ja niitä verrattiin mittaustuloksiin. Mallit näyttävät toimivan hyvin ja tuottavan vierekkäisen kanavan tehosuhteen (ACPR) -53,5dBc alemmalla kanavalla ja -53,3dBc ylemmällä kanavalla 100MHz signaalilla