Multilevel MPSoC Performance Evaluation: New ISSPT Model

To deploy the enormous hardware resources available in Multi Processor Systems-on-Chip (MPSoC) efficiently, rapidly and accurately, methods of Design Space Exploration (DSE) are needed to evaluate the different design alternatives. In this paper, we present a framework that makes fast simulation and performance evaluation of MPSoC possible early in the design flow, thus reducing the time-to-market. In this framework and within the Transaction Level Modeling (TLM) approach, we present a new definition of ISS level by introducing two complementary modeling sublevels ISST and ISSPT. This later, that we illustrate an arbiter modeling approach that allows a high performance MPSoC communication. A round-robin method is chosen because it is simple, minimizes the communication latency and has an accepted speed-up. Two applications are tested and used to validate our platform: Game of life and JPEG Encoder. The performance of the proposed approach has been analyzed in our platform MPSoC based on multi-MicroBlaze. Simulation results show with ISSPT sublevels gives a high simulation speedup factor of up to 32 with a negligible performance estimation error margin

Methodology for Integrating Computational Tree Logic Model Checking in Unified Modelling Language Artefacts A Case Study of an Embedded Controller

A unified modelling language (UML) based formal verification methodology that can be easily integrated into an embedded system software development life cycle is suggested. The approach augments UML diagrams with formal models through an interfacing domain and adds semantics to these diagrams. The suggested methodology; commences from functional specification and use case modelling, selects the most critical behaviour where formal verification can add value to the development cycle, analyses the selected behaviour using UML state transition diagram, derives a state chart matrix from the same, and a high level language software translates the state chart matrix to a labelled transition system. Safety properties are derived from system specifications and are expressed as computation tree logic (CTL) formulae. CTL model-checking algorithm from the literature is used for model- checking. The applicability of the suggested approach is established using a safety critical embedded controller used for deployment and recovery of sensor structures from an airborne platform

Modelização de Eventos: aplicação a modelos de interação do sistema com o ambiente

Neste trabalho propõe-se um conjunto de técnicas de modelização de eventos potencialmente utilizáveis em complemento a formalismos de modela-ção (Diagramas de Estado e redes de Petri, entre outros) de sistemas a eventos discretos. São definidos eventos de entrada e eventos de saída do sistema. Os eventos de entrada são originados pela análise da evolução de sinais e (outros) eventos de entrada e permitem representar comportamentos complexos das en-tradas do sistema, enquanto os eventos de saída permitem gerar sinais e (ou-tros) eventos de saída. São propostos eventos e condições elementares que detetam comporta-mentos elementares dos sinais e também composições de eventos e condições, incluindo relações de ordem temporal, de forma a obter caracterizações mais abstratas e melhorias na legibilidade e compactação do modelo. Para representar as técnicas de modelização propostas são definidas duas sintaxes diferentes (gráfica ou textual). A definição destes dois tipos de sintaxe permite a sua integração em diferentes ambientes de desenvolvimento de sis-temas. Desta forma, a principal contribuição deste trabalho foca-se na modeliza-ção da interação do sistema com o ambiente, partindo da decomposição do mo-delo do sistema em partes de interface e de execução (que comunicam através de eventos), e da adição de uma caracterização separada das dependências e dos comportamentos dos sinais de entrada e de saída com o ambiente resultan-do numa modelação estruturada do sistema, dando, assim, origem a modelos mais compactos e mais simples de interpretar e implementar

Modelling and analysis of next generation home networks

As Home Networking grows over the next 20 years the need for accurate models for both the network and the hardware becomes apparent. In this work, these two areas are considered together to develop a combined hardware and network model for a HomePlug power line based network. This change of focus is important when the type of devices that will be running on tomorrow's home network is considered. It will have evolved from a simple network of PCs sharing an Internet connection to a large heterogeneous structure of embedded System-on-Chip devices communicating on a variety of linked network technologies.This work presents a novel combined hardware and network modelling tool that address the following areas: 1. Development of a system level model of a HomePlug power-line based network, including the fundamental network protocols, the SoC hardware and the physical channel. 2. Use the developed model to explore various system scenarios. 3. Development of alternative hardware algorithms within the design. The model developed uses a Discrete Event simulation method to allow designers to explore areas such as: 1. How does the networking hardware (i.e. the components on the SoC) interact, and what are the issues of changing the algorithms. 2. I low do the nodes on the network interact, as the traffic patterns are different to those found on traditional (office-based) networks, as there will be a greater amount of streaming media

High-level synthesis of dataflow programs for heterogeneous platforms:design flow tools and design space exploration

The growing complexity of digital signal processing applications implemented in programmable logic and embedded processors make a compelling case the use of high-level methodologies for their design and implementation. Past research has shown that for complex systems, raising the level of abstraction does not necessarily come at a cost in terms of performance or resource requirements. As a matter of fact, high-level synthesis tools supporting such a high abstraction often rival and on occasion improve low-level design. In spite of these successes, high-level synthesis still relies on programs being written with the target and often the synthesis process, in mind. In other words, imperative languages such as C or C++, most used languages for high-level synthesis, are either modified or a constrained subset is used to make parallelism explicit. In addition, a proper behavioral description that permits the unification for hardware and software design is still an elusive goal for heterogeneous platforms. A promising behavioral description capable of expressing both sequential and parallel application is RVC-CAL. RVC-CAL is a dataflow programming language that permits design abstraction, modularity, and portability. The objective of this thesis is to provide a high-level synthesis solution for RVC-CAL dataflow programs and provide an RVC-CAL design flow for heterogeneous platforms. The main contributions of this thesis are: a high-level synthesis infrastructure that supports the full specification of RVC-CAL, an action selection strategy for supporting parallel read and writes of list of tokens in hardware synthesis, a dynamic fine-grain profiling for synthesized dataflow programs, an iterative design space exploration framework that permits the performance estimation, analysis, and optimization of heterogeneous platforms, and finally a clock gating strategy that reduces the dynamic power consumption. Experimental results on all stages of the provided design flow, demonstrate the capabilities of the tools for high-level synthesis, software hardware Co-Design, design space exploration, and power optimization for reconfigurable hardware. Consequently, this work proves the viability of complex systems design and implementation using dataflow programming, not only for system-level simulation but real heterogeneous implementations

Komponentenbasierte Softwareentwicklung für datenflußorientierte eingebettete Systeme

Diese Dissertation beschäftigt sich mit den Problemen bei der Entwicklung von effizienter und zuverlässiger Software für eingebettete Systeme. Eingebettete Systeme sind inhärent nebenläufig, was mit einen Grund für ihre hohe Entwurfskomplexität darstellt. Aus dieser Nebenläufigkeit resultiert ein hoher Grad an Kommunikation zwischen den einzelnen Komponenten. Eine wichtige Forderung zur Vereinfachung des Entwurfsprozesses besteht in der getrennten Modellierung von Kommunikationsprotokollen und eigentlichen Verarbeitungsalgorithmen. Daraus resultiert eine höhere Wiederverwendbarkeit bei sich ändernden Kommunikationsstrukturen. Die Grundlage für die sogenannten Datenflußsprachen bildet eine einfache von Gilles Kahn konzipierte Sprache für Parallelverarbeitung. In dieser Sprache besteht ein System aus einer Menge sequentieller Prozesse (Komponenten), die über Fifokanäle miteinander kommunizieren. Ein Prozess ist rechenbereit, wenn seine Eingangsfifos mit entsprechenden Daten gefüllt sind. Übertragen werden physikalische Signale, die als Ströme bezeichnet werden. Ströme sind Folgen von Werten ohne explizite Zeitangaben. Das Einsatzgebiet von Datenflußsprachen liegt in der Entwicklung von Programmen zur Bild- und Signalverarbeitung, typischen Aufgaben in eingebetteten Systemen. Die Programmierung erfolgt visuell, wobei man Icons als Repräsentanten parametrisierbarer Komponenten aus einer Bibliothek auswählt und mittels Kanten (Fifos) verbindet. Ein im allgemeinen dynamischer Scheduler überwacht die Ausführung des fertiggestellten Anwendungsprogramms. Diese Arbeit schlägt ein universelleres Modell physikalischer Signale vor. Dabei werden zwei Ziele verfolgt: 1. Effiziente Kommunikation zwischen den Komponenten 2. Entwurfsbegleitende Überprüfung von Programmeigenschaften unter Verwendung komplexerer Komponentenmodelle Zur Effizienzsteigerung werden nur relevante Werte innerhalb von Strömen übertragen. Dies erhöht zwar den Mehraufwand zur Kennzeichnung des Aufbaus eines Teilstroms, in praktischen Anwendungen ist die hier vorgestellte Methode jedoch effizienter. Die Einführung neuer Signalmerkmale erlaubt unterschiedlichste Überprüfungen der Einhaltung von Typregeln durch die Eingangs- und Ausgangsströme einer Komponente. Anstelle einfacher Schaltregeln werden aufwendigere Kommunikationsprotokolle für die verschiedenen Arten von Komponenten eingeführt. Fifomaten (Fifo-Automaten) dienen als formale Grundlage. Mittels eines dezidierten Model-Checking-Verfahrens wird das Zusammenspiel der Fifomaten daraufhin untersucht, ob ein zyklischer Schedule existiert. Die Existenz eines solchen zyklischen Schedules schließt Speicherüberlauf und Deadlocks aus und garantiert darüber hinaus, daß das Programm nach endlicher Zeit wieder in die Ausgangssituation zurückfindet. Da im allgemeinen die Datenflußprogramme turingäquivalent sind, kann es allerdings zyklische Schedules geben, die das Verfahren nicht entdeckt. Mit der hier vorgestellten und implementierten Methode wird die Entwicklungszeit korrekter Datenflußprogramme deutlich reduziert. Das neue Modell physikalischer Signale macht zudem die Ausführung effizienter

Contribution au domaine de la conception d’objets communicants embarqués basse consommation et autonomes en énergie

This report proposes a synthesis of my research and teaching activities. Since 2008, as associate professor at the University of Nice Sophia Antipolis, I did my research into the MCSOC team from the LEAT laboratory. For nearly 15 years, my activity is focused on the design of embedded communicating objects, with a strong emphasis for high level approach allowing, early in the design flow, to model and optimize the performance as well as the consumed energy. Those system-level approaches are more and more relevant over the last few years and become a must-have solution for designing efficient embedded systems. My activity on energy harvesting for autonomous systems brings an original contribution to this domain and has a national and international impact. This document is organized in two parts: the first part is a synthesis of my research and teaching activity, while the second one presents in details my research work, putting in evidence my contributions and innovative aspects. The manuscript ends with a scientific overview as well as some perspectives.Ce manuscrit présente une synthèse de mes travaux de recherche. Depuis septembre 2008, date de ma nomination en tant que Maître de Conférences à l’Université de Nice Sophia Antipolis, j’ai effectué mes travaux de recherche au sein de la thématique MCSOC (Modélisation, Conception Système d’Objets Communicants) du laboratoire LEAT (Université de Nice Sophia Antipolis, UMR CNRS 7248). Depuis maintenant près de 15 ans, mes travaux de recherche s’intéressent au domaine de la conception d’objets communicants embarqués avec une évolution forte vers des approches de haut niveau d’abstraction permettant tôt dans le flot de conception, de modéliser et d’optimiser les performances et la consommation d’énergie. Ces approches de niveau système n’ont cessé de prendre de l’ampleur ces dernières années et s’installent aujourd’hui comme une solution incontournable du domaine de la conception de systèmes embarqués. Mes travaux plus spécifiques sur l’autonomie énergétique de ces systèmes apportent une contribution originale au domaine et ont un rayonnement national et international. Ce document est organisé en deux parties : la première partie propose une synthèse des travaux de recherche et d’enseignement ; la seconde présente de manière détaillée mes travaux de recherche en mettant en avant toutes ses contributions et originalités. Le manuscrit s’achève par un bilan scientifique ainsi que quelques perspectives de recherche