16 research outputs found

    On the possibilities of FSM description of parallel composition of timed finite state machines

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    ΠšΠΎΠ½Π΅Ρ‡Π½Ρ‹Π΅ Π°Π²Ρ‚ΠΎΠΌΠ°Ρ‚Ρ‹ ΡˆΠΈΡ€ΠΎΠΊΠΎ ΠΈΡΠΏΠΎΠ»ΡŒΠ·ΡƒΡŽΡ‚ΡΡ для Π°Π½Π°Π»ΠΈΠ·Π° ΠΈ синтСза дискрСтных систСм. ΠŸΡ€ΠΈ описании систСм, ΠΏΠΎΠ²Π΅Π΄Π΅Π½ΠΈΠ΅ ΠΊΠΎΡ‚ΠΎΡ€Ρ‹Ρ… зависит ΠΎΡ‚ Π²Ρ€Π΅ΠΌΠ΅Π½ΠΈ, ΠΊΠΎΠ½Π΅Ρ‡Π½Ρ‹ΠΉ Π°Π²Ρ‚ΠΎΠΌΠ°Ρ‚ Ρ€Π°ΡΡˆΠΈΡ€ΡΠ΅Ρ‚ΡΡ Π²Π²Π΅Π΄Π΅Π½ΠΈΠ΅ΠΌ Π²Ρ€Π΅ΠΌΠ΅Π½Π½Ρ‹Ρ… аспСктов ΠΈ вводится понятиС Π²Ρ€Π΅ΠΌΠ΅Π½Π½ΠΎΠ³ΠΎ Π°Π²Ρ‚ΠΎΠΌΠ°Ρ‚Π°. Π’ настоящСй ΡΡ‚Π°Ρ‚ΡŒΠ΅ рассматриваСтся ΠΏΡ€ΠΎΠ±Π»Π΅ΠΌΠ° построСния ΠΏΠ°Ρ€Π°Π»Π»Π΅Π»ΡŒΠ½ΠΎΠΉ ΠΊΠΎΠΌΠΏΠΎΠ·ΠΈΡ†ΠΈΠΈ для Π΄Π²ΡƒΡ… ΠΌΠΎΠ΄Π΅Π»Π΅ΠΉ Π²Ρ€Π΅ΠΌΠ΅Π½Π½Ρ‹Ρ… Π°Π²Ρ‚ΠΎΠΌΠ°Ρ‚ΠΎΠ², Π° ΠΈΠΌΠ΅Π½Π½ΠΎ, для Π°Π²Ρ‚ΠΎΠΌΠ°Ρ‚ΠΎΠ² с Ρ‚Π°ΠΉΠΌΠ°ΡƒΡ‚Π°ΠΌΠΈ ΠΈ Π°Π²Ρ‚ΠΎΠΌΠ°Ρ‚ΠΎΠ² с Π²Ρ€Π΅ΠΌΠ΅Π½Π½Ρ‹ΠΌΠΈ ограничСниями. Π”Π²Π΅ эти Ρ„ΠΎΡ€ΠΌΡ‹ Π²Ρ€Π΅ΠΌΠ΅Π½Π½Ρ‹Ρ… Π°Π²Ρ‚ΠΎΠΌΠ°Ρ‚ΠΎΠ² Π½Π΅ ΡΠ²Π»ΡΡŽΡ‚ΡΡ взаимозамСняСмыми ΠΈ ΡΠ²Π»ΡΡŽΡ‚ΡΡ Π±ΠΎΠ»Π΅Π΅ частными случаями ΠΎΠ±Ρ‰Π΅ΠΉ ΠΌΠΎΠ΄Π΅Π»ΠΈ Π²Ρ€Π΅ΠΌΠ΅Π½Π½ΠΎΠ³ΠΎ Π°Π²Ρ‚ΠΎΠΌΠ°Ρ‚Π°, содСрТащСго ΠΊΠ°ΠΊ Ρ‚Π°ΠΉΠΌΠ°ΡƒΡ‚Ρ‹, Ρ‚Π°ΠΊ ΠΈ Π²Ρ€Π΅ΠΌΠ΅Π½Π½Ρ‹Π΅ ограничСния. ΠœΡ‹ Ρ‚Π°ΠΊΠΆΠ΅ считаСм, Ρ‡Ρ‚ΠΎ всС Π²Ρ‹ΡˆΠ΅ упомянутыС ΠΌΠΎΠ΄Π΅Π»ΠΈ Π²Ρ€Π΅ΠΌΠ΅Π½Π½Ρ‹Ρ… Π°Π²Ρ‚ΠΎΠΌΠ°Ρ‚ΠΎΠ² ΠΈΠΌΠ΅ΡŽΡ‚ цСлочислСнныС Π²Ρ‹Ρ…ΠΎΠ΄Π½Ρ‹Π΅ Π·Π°Π΄Π΅Ρ€ΠΆΠΊΠΈ (Π²Ρ‹Ρ…ΠΎΠ΄Π½Ρ‹Π΅ Ρ‚Π°ΠΉΠΌΠ°ΡƒΡ‚Ρ‹). Автоматы-ΠΊΠΎΠΌΠΏΠΎΠ½Π΅Π½Ρ‚Ρ‹ Ρ€Π°Π±ΠΎΡ‚Π°ΡŽΡ‚ Π² Ρ€Π΅ΠΆΠΈΠΌΠ΅ Π΄ΠΈΠ°Π»ΠΎΠ³Π°, ΠΏΠΎ Π·Π°Π²Π΅Ρ€ΡˆΠ΅Π½ΠΈΠΈ ΠΊΠΎΡ‚ΠΎΡ€ΠΎΠ³ΠΎ композиция Π²Ρ‹Π΄Π°Ρ‘Ρ‚ внСшний Π²Ρ‹Ρ…ΠΎΠ΄Π½ΠΎΠΉ символ. ΠŸΡ€ΠΈ Ρ€Π΅ΡˆΠ΅Π½ΠΈΠΈ Π·Π°Π΄Π°Ρ‡ Π°Π½Π°Π»ΠΈΠ·Π° для систСмы Π²Π·Π°ΠΈΠΌΠΎΠ΄Π΅ΠΉΡΡ‚Π²ΡƒΡŽΡ‰ΠΈΡ… ΠΊΠΎΠ½Π΅Ρ‡Π½Ρ‹Ρ… Π°Π²Ρ‚ΠΎΠΌΠ°Ρ‚ΠΎΠ² с использованиСм классичСских ΠΌΠ΅Ρ‚ΠΎΠ΄ΠΎΠ² такая композиция ΠΎΠ±Ρ‹Ρ‡Π½ΠΎ описываСтся СдинствСнным Π°Π²Ρ‚ΠΎΠΌΠ°Ρ‚ΠΎΠΌ. Π’ Ρ€Π°Π±ΠΎΡ‚Π΅ показываСтся, Ρ‡Ρ‚ΠΎ Π² ΠΎΠ±Ρ‰Π΅ΠΌ случаС, Π² ΠΎΡ‚Π»ΠΈΡ‡ΠΈΠ΅ ΠΎΡ‚ случая классичСских ΠΊΠΎΠ½Π΅Ρ‡Π½Ρ‹Ρ… Π°Π²Ρ‚ΠΎΠΌΠ°Ρ‚ΠΎΠ², наличия Β«ΠΌΠ΅Π΄Π»Π΅Π½Π½ΠΎΠΉ внСшнСй срСды» ΠΈ отсутствия осцилляций нСдостаточно для описания повСдСния ΠΊΠΎΠΌΠΏΠΎΠ·ΠΈΡ†ΠΈΠΈ Π΄Π΅Ρ‚Π΅Ρ€ΠΌΠΈΠ½ΠΈΡ€ΠΎΠ²Π°Π½Π½Ρ‹ΠΌ Π°Π²Ρ‚ΠΎΠΌΠ°Ρ‚ΠΎΠΌ с ΠΎΠ΄Π½ΠΎΠΉ Π²Ρ€Π΅ΠΌΠ΅Π½Π½ΠΎΠΉ ΠΏΠ΅Ρ€Π΅ΠΌΠ΅Π½Π½ΠΎΠΉ, Ссли Π²Ρ…ΠΎΠ΄Π½Ρ‹Π΅ символы ΠΌΠΎΠ³ΡƒΡ‚ ΠΏΠΎΡΡ‚ΡƒΠΏΠ°Ρ‚ΡŒ Π½Π΅ Ρ‚ΠΎΠ»ΡŒΠΊΠΎ Π² цСлочислСнныС, Π½ΠΎ ΠΈ Ρ€Π°Ρ†ΠΈΠΎΠ½Π°Π»ΡŒΠ½Ρ‹Π΅ ΠΌΠΎΠΌΠ΅Π½Ρ‚Ρ‹ Π²Ρ€Π΅ΠΌΠ΅Π½ΠΈ. Π’Π΅ΠΌ Π½Π΅ ΠΌΠ΅Π½Π΅Π΅, опрСдСляСтся класс систСм, Π² ΠΊΠΎΡ‚ΠΎΡ€Ρ‹Ρ… ΠΊΠ°ΠΆΠ΄ΠΎΠ΅ внСшнСС Π²Ρ…ΠΎΠ΄Π½ΠΎΠ΅ воздСйствиС ΠΈΠ½ΠΈΡ†ΠΈΠΈΡ€ΡƒΠ΅Ρ‚ Π΄ΠΈΠ°Π»ΠΎΠ³ ΠΌΠ΅ΠΆΠ΄Ρƒ ΠΊΠΎΠΌΠΏΠΎΠ½Π΅Π½Ρ‚Π°ΠΌΠΈ, Ρ‡Ρ‚ΠΎ позволяСт ΠΎΠΏΠΈΡΠ°Ρ‚ΡŒ ΠΏΠΎΠ²Π΅Π΄Π΅Π½ΠΈΠ΅ Ρ‚Π°ΠΊΠΎΠΉ ΠΊΠΎΠΌΠΏΠΎΠ·ΠΈΡ†ΠΈΠΈ Π΄Π΅Ρ‚Π΅Ρ€ΠΌΠΈΠ½ΠΈΡ€ΠΎΠ²Π°Π½Π½Ρ‹ΠΌ Π°Π²Ρ‚ΠΎΠΌΠ°Ρ‚ΠΎΠΌ с ΠΎΠ΄Π½ΠΎΠΉ Π²Ρ€Π΅ΠΌΠ΅Π½Π½ΠΎΠΉ ΠΏΠ΅Ρ€Π΅ΠΌΠ΅Π½Π½ΠΎΠΉ. Π’ частности, рассматриваСтся ΠΏΠΎΡΠ»Π΅Π΄ΠΎΠ²Π°Ρ‚Π΅Π»ΡŒΠ½Π°Ρ композиция Π²Ρ€Π΅ΠΌΠ΅Π½Π½Ρ‹Ρ… Π°Π²Ρ‚ΠΎΠΌΠ°Ρ‚ΠΎΠ², которая удовлСтворяСт Ρ‚Π°ΠΊΠΎΠΌΡƒ ΠΎΠ³Ρ€Π°Π½ΠΈΡ‡Π΅Π½ΠΈΡŽ. Π”Ρ€ΡƒΠ³ΠΎΠ΅ ΠΎΠ³Ρ€Π°Π½ΠΈΡ‡Π΅Π½ΠΈΠ΅ ΠΏΡ€ΠΎΠ΄ΠΈΠΊΡ‚ΠΎΠ²Π°Π½ΠΎ Π½Π°Π»ΠΈΡ‡ΠΈΠ΅ΠΌ Ρ‚Π°ΠΉΠΌΠ°ΡƒΡ‚ΠΎΠ², Π·Π½Π°Ρ‡Π΅Π½ΠΈΠ΅ ΠΊΠΎΡ‚ΠΎΡ€ΠΎΠ³ΠΎ Π² ΠΊΠ°ΠΆΠ΄ΠΎΠΌ ΠΈΠ· состояний Π΄ΠΎΠ»ΠΆΠ½ΠΎ ΠΏΡ€Π΅Π²Ρ‹ΡˆΠ°Ρ‚ΡŒ Π²Π΅Π»ΠΈΡ‡ΠΈΠ½Ρƒ Π²Ρ‹Ρ…ΠΎΠ΄Π½ΠΎΠΉ Π·Π°Π΄Π΅Ρ€ΠΆΠΊΠΈ ΠΏΡ€ΠΈ ΠΎΠ±Ρ€Π°Π±ΠΎΡ‚ΠΊΠ΅ любого ΠΏΠ΅Ρ€Π΅Ρ…ΠΎΠ΄Π° Π² этом состоянии

    Bounded Determinization of Timed Automata with Silent Transitions

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    Deterministic timed automata are strictly less expressive than their non-deterministic counterparts, which are again less expressive than those with silent transitions. As a consequence, timed automata are in general non-determinizable. This is unfortunate since deterministic automata play a major role in model-based testing, observability and implementability. However, by bounding the length of the traces in the automaton, effective determinization becomes possible. We propose a novel procedure for bounded determinization of timed automata. The procedure unfolds the automata to bounded trees, removes all silent transitions and determinizes via disjunction of guards. The proposed algorithms are optimized to the bounded setting and thus are more efficient and can handle a larger class of timed automata than the general algorithms. The approach is implemented in a prototype tool and evaluated on several examples. To our best knowledge, this is the first implementation of this type of procedure for timed automata.Comment: 25 page

    Reducing Clocks in Timed Automata while Preserving Bisimulation

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    Model checking timed automata becomes increasingly complex with the increase in the number of clocks. Hence it is desirable that one constructs an automaton with the minimum number of clocks possible. The problem of checking whether there exists a timed automaton with a smaller number of clocks such that the timed language accepted by the original automaton is preserved is known to be undecidable. In this paper, we give a construction, which for any given timed automaton produces a timed bisimilar automaton with the least number of clocks. Further, we show that such an automaton with the minimum possible number of clocks can be constructed in time that is doubly exponential in the number of clocks of the original automaton.Comment: 28 pages including reference, 8 figures, full version of paper accepted in CONCUR 201

    Compositional schedulability analysis of real-time actor-based systems

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    We present an extension of the actor model with real-time, including deadlines associated with messages, and explicit application-level scheduling policies, e.g.,"earliest deadline first" which can be associated with individual actors. Schedulability analysis in this setting amounts to checking whether, given a scheduling policy for each actor, every task is processed within its designated deadline. To check schedulability, we introduce a compositional automata-theoretic approach, based on maximal use of model checking combined with testing. Behavioral interfaces define what an actor expects from the environment, and the deadlines for messages given these assumptions. We use model checking to verify that actors match their behavioral interfaces. We extend timed automata refinement with the notion of deadlines and use it to define compatibility of actor environments with the behavioral interfaces. Model checking of compatibility is computationally hard, so we propose a special testing process. We show that the analyses are decidable and automate the process using the Uppaal model checke

    Determinisability of register and timed automata

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    The deterministic membership problem for timed automata asks whether the timed language given by a nondeterministic timed automaton can be recognised by a deterministic timed automaton. An analogous problem can be stated in the setting of register automata. We draw the complete decidability/complexity landscape of the deterministic membership problem, in the setting of both register and timed automata. For register automata, we prove that the deterministic membership problem is decidable when the input automaton is a nondeterministic one-register automaton (possibly with epsilon transitions) and the number of registers of the output deterministic register automaton is fixed. This is optimal: We show that in all the other cases the problem is undecidable, i.e., when either 1) the input nondeterministic automaton has two registers or more (even without epsilon transitions), or 2) it uses guessing, or 3) the number of registers of the output deterministic automaton is not fixed. The landscape for timed automata follows a similar pattern. We show that the problem is decidable when the input automaton is a one-clock nondeterministic timed automaton without epsilon transitions and the number of clocks of the output deterministic timed automaton is fixed. Again, this is optimal: We show that the problem in all the other cases is undecidable, i.e., when either 1) the input nondeterministic timed automaton has two clocks or more, or 2) it uses epsilon transitions, or 3) the number of clocks of the output deterministic automaton is not fixed.Comment: journal version of a CONCUR'20 paper. arXiv admin note: substantial text overlap with arXiv:2007.0934

    Utilization of timed automata as a verification tool for real-time security protocols

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    Thesis (Master)--Izmir Institute of Technology, Computer Engineering, Izmir, 2010Includes bibliographical references (leaves: 85-92)Text in English; Abstract: Turkish and Englishxi, 92 leavesTimed Automata is an extension to the automata-theoretic approach to the modeling of real time systems that introduces time into the classical automata. Since it has been first proposed by Alur and Dill in the early nineties, it has become an important research area and been widely studied in both the context of formal languages and modeling and verification of real time systems. Timed automata use dense time modeling, allowing efficient model checking of time-sensitive systems whose correct functioning depend on the timing properties. One of these application areas is the verification of security protocols. This thesis aims to study the timed automata model and utilize it as a verification tool for security protocols. As a case study, the Neuman-Stubblebine Repeated Authentication Protocol is modeled and verified employing the time-sensitive properties in the model. The flaws of the protocol are analyzed and it is commented on the benefits and challenges of the model
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