Linear-Phase FIR Digital Filter ‎Design with Reduced Hardware Complexity using Discrete Differential Evolution

Optimal design of xed coe cient nite word length linear phase FIR digital lters for custom ICs has been the focus of research in the past decade. With the ever increasing demands for high throughput and low power circuits, the need to design lters with reduced hardware complexity has become more crucial. Multiplierless lters provide substantial saving in hardware by using a shift add network to generate the lter coe cients. In this thesis, the multiplierless lter design problem is modeled as combinatorial optimization problem and is solved using a discrete Di erential Evolution algorithm. The Di erential Evolution algorithm\u27s population representation adapted for the nite word length lter design problem is developed and the mutation operator is rede ned for discrete valued parameters. Experiments show that the method is able to design lters up to a length of 300 taps with reduced hardware and shorter design times

Linear-Phase FIR Digital Filter Design with Reduced Hardware Complexity using Extremal Optimization

Extremal Optimization is a recent method for solving hard optimization problems. It has been successfully applied on many optimization problems. Extremal optimization does not share the disadvantage of most of the other evolutionary algorithms, which is the tendency to converge into local minima. Design of finite word length FIR filters using deterministic techniques can guarantee optimality at the expense of exponential increase in computational complexity. Alternatively, Evolutionary Algorithms are capable of converging very fast to a minimum, but have higher chances of failure if the ratio of feasible solutions is very less in the search space. In this thesis, a set of feasible solutions are determined by linear programming. In the second step, Extremal Optimization is used to further refine these results. This strategy helps by reducing the search space for the EO algorithm and is able to find good solutions in much shorter time than the existing methods

Field-based Coordination with the Share Operator

Field-based coordination has been proposed as a model for coordinating collective adaptive systems, promoting a view of distributed computations as functions manipulating data structures spread over space and evolving over time, called computational fields. The field calculus is a formal foundation for field computations, providing specific constructs for evolution (time) and neighbor interaction (space), which are handled by separate operators (called rep and nbr, respectively). This approach, however, intrinsically limits the speed of information propagation that can be achieved by their combined use. In this paper, we propose a new field-based coordination operator called share, which captures the space-time nature of field computations in a single operator that declaratively achieves: (i) observation of neighbors' values; (ii) reduction to a single local value; and (iii) update and converse sharing to neighbors of a local variable. We show that for an important class of self-stabilising computations, share can replace all occurrences of rep and nbr constructs. In addition to conceptual economy, use of the share operator also allows many prior field calculus algorithms to be greatly accelerated, which we validate empirically with simulations of frequently used network propagation and collection algorithms

Automatisoitu vuo suodinten laitteistokuvauksen tuottamiseen

Digitaalisia suotimia käytetään signaalien käsittelyyn monilla eri tekniikan alueilla, kuten telekommunikaatiossa, kuvankäsittelyssä ja lääketieteellisissä laitteissa. Ne ovat niin yleisiä, että insinöörit käyttävät paljon aikaa ja resursseja niiden toteuttamiseen ja verifioimiseen. Koska yleisimpien suotimien rakenne on melko yksinkertainen, niiden luominen voidaan automatisoida generaattorin avulla. Tässä diplomityössä Nokia Networksin vaatimukset kartoitetaan automatisoidun suodinten laitteistokuvauksen tuottamisvuon kehittämiseksi. Erilaisia tuottamismenetelmiä vertaillaan, mutta lopulta päädytään kehittämään oma generaattori. Se luo suotimia yhdistelemällä osia käsinkirjoitetusta RTL:stä. Lopputuloksena on automatisoitu vuo, joka tukee vakiokertoimilla varustettuja, yhden tai useamman kanavan FIR-suotimia. Käyttäjän tulee syöttää kertoimet ja haluttu datanleveys Matlab-skriptiin. Ajettaessa skripti luo suotimen ja verifioi sen. Vuo tukee sekä ASIC- että FPGA-teknologioita.Digital filters are used to process signals in many fields like telecommunications, image processing and in medical equipment. They are so omnipresent that engineers are building and verifying those all the time, using a lot of resources. As the structure of a basic filter is quite simple, savings could be made by automatizing the creation of filters. In this Thesis the requirements of Nokia Networks are analyzed to build an automatized filter generation flow. Different tools are evaluated, but finally a custom generator is built. It crafts filters from pieces of hand-written RTL. The end result is an automated flow which supports single and multichannel FIR filters with constant coefficients. The user has to input the coefficients to a Matlab script with the desired data widths. The filter is then generated and verified by running the script. The flow supports both ASIC and FPGA technologies

Automatisoitu vuo suodinten laitteistokuvauksen tuottamiseen

Digitaalisia suotimia käytetään signaalien käsittelyyn monilla eri tekniikan alueilla, kuten telekommunikaatiossa, kuvankäsittelyssä ja lääketieteellisissä laitteissa. Ne ovat niin yleisiä, että insinöörit käyttävät paljon aikaa ja resursseja niiden toteuttamiseen ja verifioimiseen. Koska yleisimpien suotimien rakenne on melko yksinkertainen, niiden luominen voidaan automatisoida generaattorin avulla. Tässä diplomityössä Nokia Networksin vaatimukset kartoitetaan automatisoidun suodinten laitteistokuvauksen tuottamisvuon kehittämiseksi. Erilaisia tuottamismenetelmiä vertaillaan, mutta lopulta päädytään kehittämään oma generaattori. Se luo suotimia yhdistelemällä osia käsinkirjoitetusta RTL:stä. Lopputuloksena on automatisoitu vuo, joka tukee vakiokertoimilla varustettuja, yhden tai useamman kanavan FIR-suotimia. Käyttäjän tulee syöttää kertoimet ja haluttu datanleveys Matlab-skriptiin. Ajettaessa skripti luo suotimen ja verifioi sen. Vuo tukee sekä ASIC- että FPGA-teknologioita.Digital filters are used to process signals in many fields like telecommunications, image processing and in medical equipment. They are so omnipresent that engineers are building and verifying those all the time, using a lot of resources. As the structure of a basic filter is quite simple, savings could be made by automatizing the creation of filters. In this Thesis the requirements of Nokia Networks are analyzed to build an automatized filter generation flow. Different tools are evaluated, but finally a custom generator is built. It crafts filters from pieces of hand-written RTL. The end result is an automated flow which supports single and multichannel FIR filters with constant coefficients. The user has to input the coefficients to a Matlab script with the desired data widths. The filter is then generated and verified by running the script. The flow supports both ASIC and FPGA technologies

Computation Against a Neighbour

Recent works in contexts like the Internet of Things (IoT) and large-scale Cyber-Physical Systems (CPS) propose the idea of programming distributed systems by focussing on their global behaviour across space and time. In this view, a potentially vast and heterogeneous set of devices is considered as an "aggregate" to be programmed as a whole, while abstracting away the details of individual behaviour and exchange of messages, which are expressed declaratively. One such a paradigm, known as aggregate programming, builds on computational models inspired by field-based coordination. Existing models such as the field calculus capture interaction with neighbours by a so-called "neighbouring field" (a map from neighbours to values). This requires ad-hoc mechanisms to smoothly compose with standard values, thus complicating programming and introducing clutter in aggregate programs, libraries and domain-specific languages (DSLs). To address this key issue we introduce the novel notion of "computation against a neighbour", whereby the evaluation of certain subexpressions of the aggregate program are affected by recent corresponding evaluations in neighbours. We capture this notion in the neighbours calculus (NC), a new field calculus variant which is shown to smoothly support declarative specification of interaction with neighbours, and correspondingly facilitate the embedding of field computations as internal DSLs in common general-purpose programming languages -- as exemplified by a Scala implementation, called ScaFi. This paper formalises NC, thoroughly compares it with respect to the classic field calculus, and shows its expressiveness by means of a case study in edge computing, developed in ScaFi.Comment: 50 pages, 16 figure

OPTIMIZATION OF FPGA-BASED PROCESSOR ARCHITECTURE FOR SOBEL EDGE DETECTION OPERATOR

This dissertation introduces an optimized processor architecture for Sobel edge detection operator on field programmable gate arrays (FPGAs). The processor is optimized by the use of several optimization techniques that aim to increase the processor throughput and reduce the processor logic utilization and memory usage. FPGAs offer high levels of parallelism which is exploited by the processor to implement the parallel process of edge detection in order to increase the processor throughput and reduce the logic utilization. To achieve this, the proposed processor consists of several Sobel instances that are able to produce multiple output pixels in parallel. This parallelism enables data reuse within the processor block. Moreover, the processor gains performance with a factor equal to the number of instances contained in the processor block. The processor that consists of one row of Sobel instances exploits data reuse within one image line in the calculations of the horizontal gradient. Data reuse within one and multiple image lines is enabled by using a processor with multiple rows of Sobel instances which allow the reuse of both the horizontal and vertical gradients. By the application of the optimization techniques, the proposed Sobel processor is able to meet real-time performance constraints due to its high throughput even with a considerably low clock frequency. In addition, logic utilization of the processor is low compared to other Sobel processors when implemented on ALTERA Cyclone II DE2-70