Hierarchical Agent-based Adaptation for Self-Aware Embedded Computing Systems

Siirretty Doriast

Reconfigurable High Performance Secured NoC Design Using Hierarchical Agent-based Monitoring System

With the rapid increase in demand for high performance computing, there is also a significant growth of data communication that leads to leverage the significance of network on chip. This paper proposes a reconfigurable fault tolerant on chip architecture with hierarchical agent based monitoring system for enhancing the performance of network based multiprocessor system on chip against faulty links and nodes. These distributed agents provide healthy status and congestion information of the network. This status information is used for further packet routing in the network with the help of XY routing algorithm. The functionality of Agent is enhanced not only to work as information provider but also to take decision for packet to either pass or stop to the processing element by setting the firewall in order to provide security. Proposed design provides a better performance and area optimization by avoiding deadlock and live lock as compared to existing approaches over network design

A self-adaptive image processing application based on evolvable and scalable hardware

Evolvable Hardware (EH) is a technique that consists of using reconfigurable hardware devices whose configuration is controlled by an Evolutionary Algorithm (EA). Our system consists of a fully-FPGA implemented scalable EH platform, where the Reconfigurable processing Core (RC) can adaptively increase or decrease in size. Figure 1 shows the architecture of the proposed System-on-Programmable-Chip (SoPC), consisting of a MicroBlaze processor responsible of controlling the whole system operation, a Reconfiguration Engine (RE), and a Reconfigurable processing Core which is able to change its size in both height and width. This system is used to implement image filters, which are generated autonomously thanks to the evolutionary process. The system is complemented with a camera that enables the usage of the platform for real time applications

A novel FPGA-based evolvable hardware system based on multiple processing arrays

In this paper, an architecture based on a scalable and flexible set of Evolvable Processing arrays is presented. FPGA-native Dynamic Partial Reconfiguration (DPR) is used for evolution, which is done intrinsically, letting the system to adapt autonomously to variable run-time conditions, including the presence of transient and permanent faults. The architecture supports different modes of operation, namely: independent, parallel, cascaded or bypass mode. These modes of operation can be used during evolution time or during normal operation. The evolvability of the architecture is combined with fault-tolerance techniques, to enhance the platform with self-healing features, making it suitable for applications which require both high adaptability and reliability. Experimental results show that such a system may benefit from accelerated evolution times, increased performance and improved dependability, mainly by increasing fault tolerance for transient and permanent faults, as well as providing some fault identification possibilities. The evolvable HW array shown is tailored for window-based image processing applications

Auto-routing algorithm for field-programmable photonic gate arrays

[EN] Programmable multipurpose photonic integrated circuits require software routines to make use of their flexible operation as desired. In this work, we propose and demonstrate the use of a modified tree-search algorithm to automatically determine the optimum optical path in a field-programmable photonic gate array (FPPGA), based on end-user specifications, circuit architecture and imperfections in the realized FPPGA arising, for example, from fabrication variations. In such a scenario, the proposed algorithm only requires the hardware topology and the location of the connections of the FPPGA defining the optical path to be programmed. The routine is able to optimize the path over multiple and competing objectives like the overall length, accumulated loss and power consumption. In addition, should any region of the circuit suffer from any potential damage that may affect the device performance, this algorithm is also able to provide basic self-healing and fault-tolerance capabilities by supplying alternative paths through the photonic arrangement.The authors acknowledge financial support by the ERC ADG-2016 UMWP-Chip ERC-2016- ADG-741415, the ERC PoC-2019 FPPAs ERC-2019-POC-859927, the Generalitat Valenciana Future MWP technologies and applications PROMETEO 2017/103 research excellency award, and the COST Action CA16220 EUIMWP, the Advanced Instrumentation for World Class Microwave Photonics Research IDIFEDER/2018/031 and the Infraestructura para caracterizacion de Chips Fotonicos EQC2018-004683-PLópez-Hernández, A.; Pérez-López, D.; Dasmahapatra, P.; Capmany Francoy, J. (2020). Auto-routing algorithm for field-programmable photonic gate arrays. Optics Express. 28(1):737-752. https://doi.org/10.1364/oe.382753737752281Soref, R. (2006). The Past, Present, and Future of Silicon Photonics. IEEE Journal of Selected Topics in Quantum Electronics, 12(6), 1678-1687. doi:10.1109/jstqe.2006.883151Streshinsky, M., Ding, R., Liu, Y., Novack, A., Galland, C., Lim, A. E.-J., … Hochberg, M. (2013). The Road to Affordable, Large-Scale Silicon Photonics. Optics and Photonics News, 24(9), 32. doi:10.1364/opn.24.9.000032Smit, M., Leijtens, X., Ambrosius, H., Bente, E., van der Tol, J., Smalbrugge, B., … van Veldhoven, R. (2014). An introduction to InP-based generic integration technology. Semiconductor Science and Technology, 29(8), 083001. doi:10.1088/0268-1242/29/8/083001Carroll, L., Lee, J.-S., Scarcella, C., Gradkowski, K., Duperron, M., Lu, H., … O’Brien, P. (2016). Photonic Packaging: Transforming Silicon Photonic Integrated Circuits into Photonic Devices. Applied Sciences, 6(12), 426. doi:10.3390/app6120426Pérez, D., Gasulla, I., & Capmany, J. (2018). Field-programmable photonic arrays. Optics Express, 26(21), 27265. doi:10.1364/oe.26.027265Pérez, D., Gasulla, I., Capmany, J., & Soref, R. A. (2016). Reconfigurable lattice mesh designs for programmable photonic processors. Optics Express, 24(11), 12093. doi:10.1364/oe.24.012093Zhuang, L., Roeloffzen, C. G. H., Hoekman, M., Boller, K.-J., & Lowery, A. J. (2015). Programmable photonic signal processor chip for radiofrequency applications. Optica, 2(10), 854. doi:10.1364/optica.2.000854Pérez, D., Gasulla, I., Crudgington, L., Thomson, D. J., Khokhar, A. Z., Li, K., … Capmany, J. (2017). Multipurpose silicon photonics signal processor core. Nature Communications, 8(1). doi:10.1038/s41467-017-00714-1Pérez, D., & Capmany, J. (2019). Scalable analysis for arbitrary photonic integrated waveguide meshes. Optica, 6(1), 19. doi:10.1364/optica.6.000019Dijkstra, E. W. (1959). A note on two problems in connexion with graphs. Numerische Mathematik, 1(1), 269-271. doi:10.1007/bf01386390McQuillan, J., Richer, I., & Rosen, E. (1980). The New Routing Algorithm for the ARPANET. IEEE Transactions on Communications, 28(5), 711-719. doi:10.1109/tcom.1980.109472