Principles, fundamentals, and applications of programmable integrated photonics

[EN] Programmable integrated photonics is an emerging new paradigm that aims at designing common integrated optical hardware resource configurations, capable of implementing an unconstrained variety of functionalities by suitable programming, following a parallel but not identical path to that of integrated electronics in the past two decades of the last century. Programmable integrated photonics is raising considerable interest, as it is driven by the surge of a considerable number of new applications in the fields of telecommunications, quantum information processing, sensing, and neurophotonics, calling for flexible, reconfigurable, low-cost, compact, and low-power-consuming devices that can cooperate with integrated electronic devices to overcome the limitation expected by the demise of Moore¿s Law. Integrated photonic devices exploiting full programmability are expected to scale from application-specific photonic chips (featuring a relatively low number of functionalities) up to very complex application-agnostic complex subsystems much in the same way as field programmable gate arrays and microprocessors operate in electronics. Two main differences need to be considered. First, as opposed to integrated electronics, programmable integrated photonics will carry analog operations over the signals to be processed. Second, the scale of integration density will be several orders of magnitude smaller due to the physical limitations imposed by the wavelength ratio of electrons and light wave photons. The success of programmable integrated photonics will depend on leveraging the properties of integrated photonic devices and, in particular, on research into suitable interconnection hardware architectures that can offer a very high spatial regularity as well as the possibility of independently setting (with a very low power consumption) the interconnection state of each connecting element. Integrated multiport interferometers and waveguide meshes provide regular and periodic geometries, formed by replicating unit elements and cells, respectively. In the case of waveguide meshes, the cells can take the form of a square, hexagon, or triangle, among other configurations. Each side of the cell is formed by two integrated waveguides connected by means of a Mach¿Zehnder interferometer or a tunable directional coupler that can be operated by means of an output control signal as a crossbar switch or as a variable coupler with independent power division ratio and phase shift. In this paper, we provide the basic foundations and principles behind the construction of these complex programmable circuits. We also review some practical aspects that limit the programming and scalability of programmable integrated photonics and provide an overview of some of the most salient applications demonstrated so far.European Research Council; Conselleria d'Educació, Investigació, Cultura i Esport; Ministerio de Ciencia, Innovación y Universidades; European Cooperation in Science and Technology; Horizon 2020 Framework Programme.Pérez-López, D.; Gasulla Mestre, I.; Dasmahapatra, P.; Capmany Francoy, J. (2020). Principles, fundamentals, and applications of programmable integrated photonics. Advances in Optics and Photonics. 12(3):709-786. https://doi.org/10.1364/AOP.387155709786123Lyke, J. C., Christodoulou, C. G., Vera, G. A., & Edwards, A. H. (2015). An Introduction to Reconfigurable Systems. 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213 p.En esta tesis, se pretende abordar los problemas que conlleva la protección cibernética del Precision Time Protocol (PTP). Éste es uno de los protocolos de comunicación más sensibles de entre los considerados por los organismos de estandarización para su aplicación en las futuras Smart Grids o redes eléctricas inteligentes. PTP tiene como misión distribuir una referencia de tiempo desde un dispositivo maestro al resto de dispositivos esclavos, situados dentro de una misma red, de forma muy precisa. El protocolo es altamente vulnerable, ya que introduciendo tan sólo un error de tiempo de un microsegundo, pueden causarse graves problemas en las funciones de protección del equipamiento eléctrico, o incluso detener su funcionamiento. Para ello, se propone una nueva arquitectura System-on-Chip basada en dispositivos reconfigurables, con el objetivo de integrar el protocolo PTP y el conocido estándar de seguridad MACsec para redes Ethernet. La flexibilidad que los modernos dispositivos reconfigurables proporcionan, ha sido aprovechada para el diseño de una arquitectura en la que coexisten procesamiento hardware y software. Los resultados experimentales avalan la viabilidad de utilizar MACsec para proteger la sincronización en entornos industriales, sin degradar la precisión del protocolo

Time-bin encoding for optical quantum computing

Scalability has been a longstanding issue in implementing large-scale photonic experiments for optical quantum computing. Traditional encodings based on the polarisation or spatial degrees of freedom become extremely resource-demanding when the number of modes becomes large, as the need for many nonclassical sources of light and the number of beam splitters required become unfeasible. Alternatively, time-bin encoding paves the way to overcome some of these limitations, as it only requires a single quantum light source and can be scaled to many temporal modes through judicious choice of pulse sequence and delays. Such an apparatus constitutes an important step toward large-scale experiments with low resource consumption. This work focuses on the time-bin encoding implementation. First, we assess its feasibility by thoroughly investigating its performance through numerical simulations under realistic conditions. We identify the critical components of the architecture and find that it can achieve performances comparable to state-of-the-art devices. Moreover, we consider two implementation approaches, in fibre and free space, and enumerate their strengths and weaknesses. Subsequently, we delve into the lab to explore these schemes and the key components involved therein. For the fibre case, we report the first implementation of time-bin encoded Gaussian boson sampling and use the samples obtained from the device to search for dense subgraphs of sizes three and four in a 10-node graph. Finally, we complement the study of the time-bin encoding with two side projects that contribute to the broad spectrum of enabling techniques for quantum information science. First, we demonstrate the ability to perform photon-number resolving measurements with a commercial superconducting nanowire single-photon detector system and apply it to improve the statistics of a heralded single-photon source. Second, we demonstrate that by employing a phase-tunable coherent state, we can fully characterise a multimode Gaussian state through solely the low-order photon statistics.Open Acces

Towards Energy-Efficient and Reliable Computing: From Highly-Scaled CMOS Devices to Resistive Memories

The continuous increase in transistor density based on Moore\u27s Law has led us to highly scaled Complementary Metal-Oxide Semiconductor (CMOS) technologies. These transistor-based process technologies offer improved density as well as a reduction in nominal supply voltage. An analysis regarding different aspects of 45nm and 15nm technologies, such as power consumption and cell area to compare these two technologies is proposed on an IEEE 754 Single Precision Floating-Point Unit implementation. Based on the results, using the 15nm technology offers 4-times less energy and 3-fold smaller footprint. New challenges also arise, such as relative proportion of leakage power in standby mode that can be addressed by post-CMOS technologies. Spin-Transfer Torque Random Access Memory (STT-MRAM) has been explored as a post-CMOS technology for embedded and data storage applications seeking non-volatility, near-zero standby energy, and high density. Towards attaining these objectives for practical implementations, various techniques to mitigate the specific reliability challenges associated with STT-MRAM elements are surveyed, classified, and assessed herein. Cost and suitability metrics assessed include the area of nanomagmetic and CMOS components per bit, access time and complexity, Sense Margin (SM), and energy or power consumption costs versus resiliency benefits. In an attempt to further improve the Process Variation (PV) immunity of the Sense Amplifiers (SAs), a new SA has been introduced called Adaptive Sense Amplifier (ASA). ASA can benefit from low Bit Error Rate (BER) and low Energy Delay Product (EDP) by combining the properties of two of the commonly used SAs, Pre-Charge Sense Amplifier (PCSA) and Separated Pre-Charge Sense Amplifier (SPCSA). ASA can operate in either PCSA or SPCSA mode based on the requirements of the circuit such as energy efficiency or reliability. Then, ASA is utilized to propose a novel approach to actually leverage the PV in Non-Volatile Memory (NVM) arrays using Self-Organized Sub-bank (SOS) design. SOS engages the preferred SA alternative based on the intrinsic as-built behavior of the resistive sensing timing margin to reduce the latency and power consumption while maintaining acceptable access time

Heuristics Based Test Overhead Reduction Techniques in VLSI Circuits

The electronic industry has evolved at a mindboggling pace over the last five decades. Moore’s Law [1] has enabled the chip makers to push the limits of the physics to shrink the feature sizes on Silicon (Si) wafers over the years. A constant push for power-performance-area (PPA) optimization has driven the higher transistor density trends. The defect density in advanced process nodes has posed a challenge in achieving sustainable yield. Maintaining a low Defect-per-Million (DPM) target for a product to be viable with stringent Time-to-Market (TTM) has become one of the most important aspects of the chip manufacturing process. Design-for-Test (DFT) plays an instrumental role in enabling low DPM. DFT however impacts the PPA of a chip. This research describes an approach of minimizing the scan test overhead in a chip based on circuit topology heuristics. These heuristics are applied on a full-scan design to convert a subset of the scan flip-flops (SFF) into D flip-flops (DFF). The K Longest Path per Gate (KLPG) [2] automatic test pattern generation (ATPG) algorithm is used to generate tests for robust paths in the circuit. Observability driven multi cycle path generation [3][4] and test are used in this work to minimize coverage loss caused by the SFF conversion process. The presence of memory arrays in a design exacerbates the coverage loss due to the shadow cast by the array on its neighboring logic. A specialized behavioral modeling for the memory array is required to enable test coverage of the shadow logic. This work develops a memory model integrated into the ATPG engine for this purpose. Multiple clock domains pose challenges in the path generation process. The inter-domain clocking relationship and corresponding logic sensitization are modeled in our work to generate synchronous inter-domain paths over multiple clock cycles. Results are demonstrated on ISCAS89 and ITC99 benchmark circuits. Power saving benefit is quantified using an open-source standard-cell library

System-on-chip architecture for secure sub-microsecond synchronization systems

213 p.En esta tesis, se pretende abordar los problemas que conlleva la protección cibernética del Precision Time Protocol (PTP). Éste es uno de los protocolos de comunicación más sensibles de entre los considerados por los organismos de estandarización para su aplicación en las futuras Smart Grids o redes eléctricas inteligentes. PTP tiene como misión distribuir una referencia de tiempo desde un dispositivo maestro al resto de dispositivos esclavos, situados dentro de una misma red, de forma muy precisa. El protocolo es altamente vulnerable, ya que introduciendo tan sólo un error de tiempo de un microsegundo, pueden causarse graves problemas en las funciones de protección del equipamiento eléctrico, o incluso detener su funcionamiento. Para ello, se propone una nueva arquitectura System-on-Chip basada en dispositivos reconfigurables, con el objetivo de integrar el protocolo PTP y el conocido estándar de seguridad MACsec para redes Ethernet. La flexibilidad que los modernos dispositivos reconfigurables proporcionan, ha sido aprovechada para el diseño de una arquitectura en la que coexisten procesamiento hardware y software. Los resultados experimentales avalan la viabilidad de utilizar MACsec para proteger la sincronización en entornos industriales, sin degradar la precisión del protocolo

System-on-chip architecture for secure sub-microsecond synchronization systems

213 p.En esta tesis, se pretende abordar los problemas que conlleva la protección cibernética del Precision Time Protocol (PTP). Éste es uno de los protocolos de comunicación más sensibles de entre los considerados por los organismos de estandarización para su aplicación en las futuras Smart Grids o redes eléctricas inteligentes. PTP tiene como misión distribuir una referencia de tiempo desde un dispositivo maestro al resto de dispositivos esclavos, situados dentro de una misma red, de forma muy precisa. El protocolo es altamente vulnerable, ya que introduciendo tan sólo un error de tiempo de un microsegundo, pueden causarse graves problemas en las funciones de protección del equipamiento eléctrico, o incluso detener su funcionamiento. Para ello, se propone una nueva arquitectura System-on-Chip basada en dispositivos reconfigurables, con el objetivo de integrar el protocolo PTP y el conocido estándar de seguridad MACsec para redes Ethernet. La flexibilidad que los modernos dispositivos reconfigurables proporcionan, ha sido aprovechada para el diseño de una arquitectura en la que coexisten procesamiento hardware y software. Los resultados experimentales avalan la viabilidad de utilizar MACsec para proteger la sincronización en entornos industriales, sin degradar la precisión del protocolo

Application of advanced on-board processing concepts to future satellite communications systems

An initial definition of on-board processing requirements for an advanced satellite communications system to service domestic markets in the 1990's is presented. An exemplar system architecture with both RF on-board switching and demodulation/remodulation baseband processing was used to identify important issues related to system implementation, cost, and technology development