2,052 research outputs found
Limits on Fundamental Limits to Computation
An indispensable part of our lives, computing has also become essential to
industries and governments. Steady improvements in computer hardware have been
supported by periodic doubling of transistor densities in integrated circuits
over the last fifty years. Such Moore scaling now requires increasingly heroic
efforts, stimulating research in alternative hardware and stirring controversy.
To help evaluate emerging technologies and enrich our understanding of
integrated-circuit scaling, we review fundamental limits to computation: in
manufacturing, energy, physical space, design and verification effort, and
algorithms. To outline what is achievable in principle and in practice, we
recall how some limits were circumvented, compare loose and tight limits. We
also point out that engineering difficulties encountered by emerging
technologies may indicate yet-unknown limits.Comment: 15 pages, 4 figures, 1 tabl
Fault and Defect Tolerant Computer Architectures: Reliable Computing With Unreliable Devices
This research addresses design of a reliable computer from unreliable device technologies. A system architecture is developed for a fault and defect tolerant (FDT) computer. Trade-offs between different techniques are studied and yield and hardware cost models are developed. Fault and defect tolerant designs are created for the processor and the cache memory. Simulation results for the content-addressable memory (CAM)-based cache show 90% yield with device failure probabilities of 3 x 10(-6), three orders of magnitude better than non fault tolerant caches of the same size. The entire processor achieves 70% yield with device failure probabilities exceeding 10(-6). The required hardware redundancy is approximately 15 times that of a non-fault tolerant design. While larger than current FT designs, this architecture allows the use of devices much more likely to fail than silicon CMOS. As part of model development, an improved model is derived for NAND Multiplexing. The model is the first accurate model for small and medium amounts of redundancy. Previous models are extended to account for dependence between the inputs and produce more accurate results
Simulation and Modeling of Silicon Based Emerging Nanodevices: From Device to Circuit Level
Nanostructure based devices are very promising candidates for the emerging
nanotechnologies with advantage in terms of power consumption and functional
density. Nanowire Field Effect Transistor (NWFET) and Single Electron Transistor
(SET) are the focus of this work. The serious challenges faced by the MOSFET
due to scaling limits can be solved by these devices. NWFET provides better gate
control and overcomes the short channel effects. SET operates in the quantum
confinement regime where the basic operation of MOSFET becomes a challenge.
SET works better when the dimensions are small encouraging the process of scaling
down. Because of these characteristics of the nanodevices, they have achieved a
huge interest from the viewpoint of theoretical as well as applied electronics. The
studies focus on the understanding of the basic transport characteristics of the
devices. The necessity is to develop a model which is efficient, can be used at
circuit level and also provides physical insights of the device.
The first part of this work focuses on developing the model for SET and to
implement it at the circuit level. The transport properties of SET are studied
through quantum simulations. The behavioral characterization of the device is
performed and the effect of different device parameters on the transport is studied.
Furthermore, the impact of gate voltage is analyzed which modulates the current
by shifting the energy levels of the device. After observing the transport through
SET, a model is developed that efficiently evaluates the IV characteristics of the
device. The quantum simulations are used as reference and a huge computational
over-head is achieved while maintaining accuracy. Then the model is implemented
in hardware descriptive language showing its functional variability at circuit level
by designing some logic circuits like AND, OR and FA.
In the second part, the performance of the nanoarrays based on NWFET is
characterized. A device level model is developed to evaluate the gate capacitance
and drain current of NWFET. Starting from the output of the model, in-house simulator is modified and used to evaluate the switching activity of the devices
in nanoarray. A nanoarray implementation for bio-sequence alignment based on
a systolic array is realized and its essential performance is evaluated. The power
consumption, area and performance of the nanoarray implementation are compared
with CMOS implementation. A wide solution space can be explored to find the
optimal solution trading power and performance and considering the technological
limitations of a realistic implementation
Product assurance technology for procuring reliable, radiation-hard, custom LSI/VLSI electronics
Advanced measurement methods using microelectronic test chips are described. These chips are intended to be used in acquiring the data needed to qualify Application Specific Integrated Circuits (ASIC's) for space use. Efforts were focused on developing the technology for obtaining custom IC's from CMOS/bulk silicon foundries. A series of test chips were developed: a parametric test strip, a fault chip, a set of reliability chips, and the CRRES (Combined Release and Radiation Effects Satellite) chip, a test circuit for monitoring space radiation effects. The technical accomplishments of the effort include: (1) development of a fault chip that contains a set of test structures used to evaluate the density of various process-induced defects; (2) development of new test structures and testing techniques for measuring gate-oxide capacitance, gate-overlap capacitance, and propagation delay; (3) development of a set of reliability chips that are used to evaluate failure mechanisms in CMOS/bulk: interconnect and contact electromigration and time-dependent dielectric breakdown; (4) development of MOSFET parameter extraction procedures for evaluating subthreshold characteristics; (5) evaluation of test chips and test strips on the second CRRES wafer run; (6) two dedicated fabrication runs for the CRRES chip flight parts; and (7) publication of two papers: one on the split-cross bridge resistor and another on asymmetrical SRAM (static random access memory) cells for single-event upset analysis
Quantum Computing
Quantum mechanics---the theory describing the fundamental workings of
nature---is famously counterintuitive: it predicts that a particle can be in
two places at the same time, and that two remote particles can be inextricably
and instantaneously linked. These predictions have been the topic of intense
metaphysical debate ever since the theory's inception early last century.
However, supreme predictive power combined with direct experimental observation
of some of these unusual phenomena leave little doubt as to its fundamental
correctness. In fact, without quantum mechanics we could not explain the
workings of a laser, nor indeed how a fridge magnet operates. Over the last
several decades quantum information science has emerged to seek answers to the
question: can we gain some advantage by storing, transmitting and processing
information encoded in systems that exhibit these unique quantum properties?
Today it is understood that the answer is yes. Many research groups around the
world are working towards one of the most ambitious goals humankind has ever
embarked upon: a quantum computer that promises to exponentially improve
computational power for particular tasks. A number of physical systems,
spanning much of modern physics, are being developed for this task---ranging
from single particles of light to superconducting circuits---and it is not yet
clear which, if any, will ultimately prove successful. Here we describe the
latest developments for each of the leading approaches and explain what the
major challenges are for the future.Comment: 26 pages, 7 figures, 291 references. Early draft of Nature 464, 45-53
(4 March 2010). Published version is more up-to-date and has several
corrections, but is half the length with far fewer reference
Electrical overstress and electrostatic discharge failure in silicon MOS devices
This thesis presents an experimental and theoretical investigation of electrical failure
in MOS structures, with a particular emphasis on short-pulse and ESD failure. It begins with
an extensive survey of MOS technology, its failure mechanisms and protection schemes. A
program of experimental research on MOS breakdown is then reported, the results of which
are used to develop a model of breakdown across a wide spectrum of time scales. This
model, in which bulk-oxide electron trapping/emission plays a major role, prohibits the direct
use of causal theory over short time-scales, invalidating earlier theories on the subject.
The work is extended to ESD stress of both polarities. Negative polarity ESD
breakdownis found to be primarily oxide-voltage activated, with no significant dependence
on temperature of luminosity. Positive polarity breakdown depends on the rate of surface
inversion, dictated by the Si avalanche threshold and/or the generation speed of light-induced
carriers. An analytical model, based upon the above theory is developed to predict ESD
breakdown over a wide range of conditions.
The thesis ends with an experimental and theoretical investigation of the effects of
ESD breakdown on device and circuit performance. Breakdown sites are modelled as
resistive paths in the oxide, and their distorting effects upon transistor performance are
studied. The degradation of a damaged transistor under working stress is observed, giving
a deeper insight into the latent hazards of ESD damage
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Roadmap on quantum nanotechnologies
Quantum phenomena are typically observable at length and time scales smaller than those of our everyday experience, often involving individual particles or excitations. The past few decades have seen a revolution in the ability to structure matter at the nanoscale, and experiments at the single particle level have become commonplace. This has opened wide new avenues for exploring and harnessing quantum mechanical effects in condensed matter. These quantum phenomena, in turn, have the potential to revolutionize the way we communicate, compute and probe the nanoscale world. Here, we review developments in key areas of quantum research in light of the nanotechnologies that enable them, with a view to what the future holds. Materials and devices with nanoscale features are used for quantum metrology and sensing, as building blocks for quantum computing, and as sources and detectors for quantum communication. They enable explorations of quantum behaviour and unconventional states in nano- and opto-mechanical systems, low-dimensional systems, molecular devices, nano-plasmonics, quantum electrodynamics, scanning tunnelling microscopy, and more. This rapidly expanding intersection of nanotechnology and quantum science/technology is mutually beneficial to both fields, laying claim to some of the most exciting scientific leaps of the last decade, with more on the horizon
Miniaturized Transistors, Volume II
In this book, we aim to address the ever-advancing progress in microelectronic device scaling. Complementary Metal-Oxide-Semiconductor (CMOS) devices continue to endure miniaturization, irrespective of the seeming physical limitations, helped by advancing fabrication techniques. We observe that miniaturization does not always refer to the latest technology node for digital transistors. Rather, by applying novel materials and device geometries, a significant reduction in the size of microelectronic devices for a broad set of applications can be achieved. The achievements made in the scaling of devices for applications beyond digital logic (e.g., high power, optoelectronics, and sensors) are taking the forefront in microelectronic miniaturization. Furthermore, all these achievements are assisted by improvements in the simulation and modeling of the involved materials and device structures. In particular, process and device technology computer-aided design (TCAD) has become indispensable in the design cycle of novel devices and technologies. It is our sincere hope that the results provided in this Special Issue prove useful to scientists and engineers who find themselves at the forefront of this rapidly evolving and broadening field. Now, more than ever, it is essential to look for solutions to find the next disrupting technologies which will allow for transistor miniaturization well beyond silicon’s physical limits and the current state-of-the-art. This requires a broad attack, including studies of novel and innovative designs as well as emerging materials which are becoming more application-specific than ever before
Cutting Edge Nanotechnology
The main purpose of this book is to describe important issues in various types of devices ranging from conventional transistors (opening chapters of the book) to molecular electronic devices whose fabrication and operation is discussed in the last few chapters of the book. As such, this book can serve as a guide for identifications of important areas of research in micro, nano and molecular electronics. We deeply acknowledge valuable contributions that each of the authors made in writing these excellent chapters
Challenges and Opportunities in Implementing Negative Differential Resistance Mode Reconfigurable Field Effect Transistors
Desirably, the world relies on the devices being compact, as they could drive
to the increased functionality of integrated circuits at the provided footstep,
that is becoming more reliable. To reduce the scalability over the devices,
approach has been outlined utilizing the NDR mode reconfigurable functionality
over the transistors. Being an individual device efficient in exhibiting
different task with the different configurations in the same physical
circuitry. On the view of reconfigurable transistors, possibly authorize the
reconfiguration from a p-type to n-type channel transistor has been expelled as
an emerging application such as static memory cells, fast switching logic
circuits as well as energy efficient computational multi valued logic. This
article emphasizes NDR mode RFET along with its classification, followed by
enhancing the RFET technology concepts and RFETs future potential has been
discussed briefing with the growing applications like hardware security as well
as neuro-inspired computing.Comment: 28 pages, 9 figure
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