The java.util.concurrent synchronizer framework

AbstractMost synchronizers (locks, barriers, etc.) in the J2SE 5.0 java.util.concurrent package are constructed using a small framework based on class AbstractQueuedSynchronizer. This framework provides common mechanics for atomically managing synchronization state, blocking and unblocking threads, and queuing. The paper describes the rationale, design, implementation, usage, and performance of this framework

Constant RMR Solutions to Reader Writer Synchronization

We study Reader-Writer Exclusion, a well-known variant of the Mutual Exclusion problem where processes are divided into two classes--readers and writers--and multiple readers can be in the Critical Section (CS) at the same time, although no process may be in the CS at the same time as a writer. Since readers don\u27t conflict with each other, they should not obstruct each other. Specifically, the concurrent entering property must be satisfied: if all writers are in the remainder section, each reader should be able to enter the CS in a bounded number of its own steps. Three versions of the Reader-Writer Exclusion problem are commonly studied--one where writers have priority over readers, another where readers have priority, and the last where neither class has priority over the other and no process may starve. To ensure high performance on Cache-Coherent (CC) and Distributed Shared Memory (DSM) multiprocessors, algorithms should be designed to generate as few remote memory references (RMRs) as possible. The ideal would be to achieve constant RMR complexity, i.e., the worst case number of RMRs that a process generates in order to enter and exit the CS once is a constant, independent of the number of processes. Constant RMR complexity algorithms have existed for Mutual Exclusion for two decades, but none exists for Reader-Writer Exclusion. Danek and Hadzilacos\u27 lower bound proof implies that it is impossible to achieve sublinear RMR complexity for DSM machines. For CC machines, the best existing bound, also due to Danek and Hadzilacos , is O(log n), where n is the number of processes. In this work, we present the first constant RMR complexity algorithms for all three versions of the Reader-Writer Exclusion problem (for CC machines)

Customizable Operating Systems

A customizable operating system is one that can adapt to improve its functionality or performance. The need for customizable and application-specific operating systems has been recognized for many years, but they have yet to appear in the commercial market. This paper explores the notion of operating system customizability and examines the limits of existing approaches. The paper begins by surveying system structuring approaches for the safe and efficient execution of customizable operating systems. Then it discusses the burden that existing approaches impose on application software, and explores techniques for reducing this burden. Finally, support for customizability in the Synthetix project is described and illustrated through two examples: a dynamically specialized file system read call, and an adaptive Internet-based MPEG video player

Concurrent Scheme

Journal ArticleThis paper describes an evolution of the Scheme language to support parallelism with tight coupling of control and data. Mechanisms are presented to address the difficult and related problems of mutual exclusion and data sharing which arise in concurrent language systems. The mechanisms are tailored to preserve Scheme semantics as much as possible while allowing for efficient implementation. Prototype implementations of the resulting language are described which have been completed. A third implementation is underway for the Mayfly, a distributed memory, twisted-torus communication topology, parallel processor, under development at the Hewlett-Packard Research Laboratories. The language model is particularly well suited for the Mayfly processor, as will be shown

Scheduling Techniques for Operating Systems for Medical and IoT Devices: A Review

Software and Hardware synthesis are the major subtasks in the implementation of hardware/software systems. Increasing trend is to build SoCs/NoC/Embedded System for Implantable Medical Devices (IMD) and Internet of Things (IoT) devices, which includes multiple Microprocessors and Signal Processors, allowing designing complex hardware and software systems, yet flexible with respect to the delivered performance and executed application. An important technique, which affect the macroscopic system implementation characteristics is the scheduling of hardware operations, program instructions and software processes. This paper presents a survey of the various scheduling strategies in process scheduling. Process Scheduling has to take into account the real-time constraints. Processes are characterized by their timing constraints, periodicity, precedence and data dependency, pre-emptivity, priority etc. The affect of these characteristics on scheduling decisions has been described in this paper

A multi-microcomputer intercommunication structure and multi-tasking algorithm

A recursive interconnection structure for multiple microcomputer systems is described. The average path length through such structures was computed, and the results were used as a measure of performance. Other characteristics such as flexibility, locality and complexity were also considered. An experimental dual-processor configuration was constructed and programmed to execute a producer-consumer multi-tasking algorithm, using a semaphore-protected queuing system in shared memory. The execution time was recorded, and was compared to the execution time of an optimized uniprocessor program. The results indicated that multiple microcomputer systems in general, and recursive structures in particular, are very promising, provided that sufficient attention is paid to task partitioning and interprocessor communications