Reliability evaluation of hermetic dual in-line flat microcircuit packages

The relative strengths and weaknesses of 35 commonly used hermetic flat and dual in-line packages were determined and used to rank each of the packages according to a numerical weighting scheme for package attributes. The list of attributes included desirable features in five major areas: lead and lead seal, body construction, body materials, lid and lid seal, and marking. The metal flat pack and multilayer integral ceramic flat pack and DIP received the highest rankings, and the soft glass Cerdip and Cerpak types received the lowest rankings. Loss of package hermeticity due to lead and lid seal problems was found to be the predominant failure mode from the literature/data search. However, environmental test results showed that lead and lid seal failures due to thermal stressing was only a problem with the hard glass (Ceramic) body DIP utilizing a metal lid and/or bottom. Insufficient failure data were generated for the other package types tested to correlate test results with the package ranking

Contamination Control in Hybrid Microelectronic Modules. Part 1: Identification of Critical Process and Contaminants

Various hybrid processing steps, handling procedures, and materials are examined in an attempt to identify sources of contamination and to propose methods for the control of these contaminants. It is found that package sealing, assembly, and rework are especially susceptible to contamination. Moisture and loose particles are identified as the worst contaminants. The points at which contaminants are most likely to enter the hybrid package are also identified, and both general and specific methods for their detection and control are developed. In general, the most effective controls for contaminants are: clean working areas, visual inspection at each step of the process, and effective cleaning at critical process steps. Specific methods suggested include the detection of loose particles by a precap visual inspection, by preseal and post-seal electrical testing, and by a particle impact noise test. Moisture is best controlled by sealing all packages in a clean, dry, inert atmosphere after a thorough bake-out of all parts

Influence of material quality and process-induced defects on semiconductor device performance and yield

An overview of major causes of device yield degradation is presented. The relationships of device types to critical processes and typical defects are discussed, and the influence of the defect on device yield and performance is demonstrated. Various defect characterization techniques are described and applied. A correlation of device failure, defect type, and cause of defect is presented in tabular form with accompanying illustrations

Determination of Bond Wire Failure Probabilities in Microelectronic Packages

This work deals with the computation of industry-relevant bond wire failure probabilities in microelectronic packages. Under operating conditions, a package is subject to Joule heating that can lead to electrothermally induced failures. Manufacturing tolerances result, e.g., in uncertain bond wire geometries that often induce very small failure probabilities requiring a high number of Monte Carlo (MC) samples to be computed. Therefore, a hybrid MC sampling scheme that combines the use of an expensive computer model with a cheap surrogate is used. The fraction of surrogate evaluations is maximized using an iterative procedure, yielding accurate results at reduced cost. Moreover, the scheme is non-intrusive, i.e., existing code can be reused. The algorithm is used to compute the failure probability for an example package and the computational savings are assessed by performing a surrogate efficiency study.Comment: submitted to Therminic 2016, available at http://ieeexplore.ieee.org/document/7748645

Reliability handbook for silicon monolithic microcircuits. Volume 2 - Failure mechanisms of monolithic microcircuits

Reliability handbook for silicon monolithic microcircuits - failure mechanism

The Importance of Interconnection Technologies’ Reliability of Power Electronic Packages

This chapter deals with the reliability of die interconnections used in plastic discrete power packages, dedicated to on‐board electronic systems used in a wide range of applications such as automotive industry. A complete reliability analysis of two bonding technologies—aluminum wire and ribbon bonding—is proposed. This study is particularly focused on interconnection technologies’ aging, when the package is subjected to thermal cycling or power cycling with high‐temperature swings. For thermal cycling, the experimental reliability test results highlight that wire bond package aging is about 2.5 faster than the ribbon bond package. For power cycling, this acceleration factor is about 1.5. In both cases and whatever the bonding technique, the failure mechanism of the package is of a fatigue‐stress nature. Many failure analysis results show wire bond lift‐off. The degradation of the ribbon bond is more difficult to observe. Thermo‐mechanical simulations using finite elements show a high stress concentration in the heel area. For the wire‐bonding technique, the wire is subjected to repeated flexing and pulling that lead to its lift off. The ribbon‐bonding process shows a higher robustness, thanks to a higher contact surface on the die, the low‐loop profile and the stiffness of the ribbon

The impact of repetitive unclamped inductive switching on the electrical parameters of low-voltage trench power nMOSFETs

The impact of hot-carrier injection (HCI) due to repetitive unclamped inductive switching (UIS) on the electrical performance of low-voltage trench power n-type MOSFETs (nMOSFETs) is assessed. Trench power nMOSFETs with 20- and 30-V breakdown voltage ratings in TO-220 packages have been fabricated and subjected to over 100 million cycles of repetitive UIS with different avalanche currents IAV at a mounting base temperature TMB of 150°C. Impact ionization during avalanche conduction in the channel causes hot-hole injection into the gate dielectric, which results in a reduction of the threshold voltage VGSTX, as the number of avalanche cycles N increases. The experimental data reveal a power-law relationship between the change in the threshold voltage ΔVGSTX and N. The results show that the power-law prefactor is directly proportional to the avalanche current. After 100 million cycles, it was observed in the 20-V rated MOSFETs that the power-law prefactor increased by 30% when IAV was increased from 160 to 225 A, thereby approximating a linear relationship. A stable subthreshold slope with avalanche cycling indicates that interface trap generation may not be an active degradation mechanism. The impact of the cell pitch on avalanche ruggedness is also investigated by testing 2.5- and 4- m cell-pitch 30-V rated MOSFETs. Measurements showed that the power-law prefactor reduced by 40% when the cell pitch was reduced by 37.5%. The improved VGSTX stability with the smaller cell-pitch MOSFETs is attributed to a lower avalanche current per unit cell resulting in less hot-hole injection and, hence, smaller VGSTX shift. The 2.5-m cell-pitch MOSFETs also show 25% improved on -state resistance RDSON, better RDSON stability, and 20% less subthreshold slope compared with the 4-m cell-pitch MOSFETs, although with 100% higher initial IDSS and less IDSS stability with avalanche cycling. These results are important for manufacturers of automotive MOSFETs where multiple avalanche occurrences over the lifetime of the MOSFET are expected

Study to develop process controls for line certification on hybrid microcircuits Final report, Nov. 1970 - Feb. 1971

Basic process steps for fabrication of thick or thin film microcircuits for NASA us

End-of-Life and Constant Rate Reliability Modeling for Semiconductor Packages Using Knowledge-Based Test Approaches

End-of-life and constant rate reliability modeling for semiconductor packages are the focuses of this dissertation. Knowledge-based testing approaches are applied and the test-to-failure approach is approved to be a reliable approach. First of all, the end-of-life AF models for solder joint reliability are studied. The research results show using one universal AF model for all packages is flawed approach. An assessment matrix is generated to guide the application of AF models. The AF models chosen should be either assessed based on available data or validated through accelerated stress tests. A common model can be applied if the packages have similar structures and materials. The studies show that different AF models will be required for SnPb solder joints and SAC lead-free solder joints. Second, solder bumps under power cycling conditions are found to follow constant rate reliability models due to variations of the operating conditions. Case studies demonstrate that a constant rate reliability model is appropriate to describe non solder joint related semiconductor package failures as well. Third, the dissertation describes the rate models using Chi-square approach cannot correlate well with the expected failure mechanisms in field applications. The estimation of the upper bound using a Chi-square value from zero failure is flawed. The dissertation emphasizes that the failure data is required for the failure rate estimation. A simple but tighter approach is proposed and provides much tighter bounds in comparison of other approaches available. Last, the reliability of solder bumps in flip chip packages under power cycling conditions is studied. The bump materials and underfill materials will significantly influence the reliability of the solder bumps. A set of comparable bump materials and the underfill materials will dramatically improve the end-of-life solder bumps under power cycling loads, and bump materials are one of the most significant factors. Comparing to the field failure data obtained, the end-of-life model does not predict the failures in the field, which is more close to an approximately constant failure rate. In addition, the studies find an improper underfill material could change the failure location from solder bump cracking to ILD cracking or BGA solder joint failures

Optimizing the reliability of power electronics module isolation substrates

Optimal design of a power electronics module isolation substrate is assessed using a combination of finite element structural mechanics analysis and response surface optimisation technique. Primary failure modes in power electronics modules include the loss of structural integrity in the ceramic substrate materials due to stresses induced through thermal cycling. Analysis of the influence of ceramic substrate design parameters is undertaken using a design of experiments approach. Finite element analysis is used to determine the stress distribution for each design, and the results are used to construct a quadratic response surface function. A particle swarm optimisation algorithm is then used to determine the optimal substrate design. Analysis of response surface function gradients is used to perform sensitivity analysis and develop isolation substrate design rules. The influence of design uncertainties introduced through manufacturing tolerances is assessed using a Monte-Carlo algorithm, resulting in a stress distribution histogram. The probability of failure caused by the violation of design constraints has been analyzed. Six geometric design parameters are considered in this work and the most important design parameters have been identified. Overall analysis results can be used to enhance the design and reliability of the component