Parallel-Pipelined-Memory (P2m) Of Blowfish Fpga-Based Radio System With Improved Power-Throughput For Secure Zigbee Transmission

Currently, the advanced encryption standard (AES) scheme is employed by most of the Institute of Electrical and Electronic Engineers (IEEE) standards to secure the data transmission of mobile devices specifically in internet of things (IoT) network. However, this scheme requires high compute platform and memory to support the encryption or decryption process which may not exist in all IoT-attached devices. In order to overcome this issue, this research work proposed an alternative cryptography scheme with improved power-throughput and reduced hardware utilization to be considered as a replacement to the existing AES. Based on the performance analysis among the symmetric cryptography schemes, the AES-128 and Blowfish schemes have been chosen to be enhanced and developed based on Zynq- 7000 field programmable gate array (FPGA) technology by using three design techniques comprised of parallel, pipelined and memory (P2M) techniques. At software level, the findings showed that the proposed Blowfish design had better performance with slices occupied and power consumption decreased by 45.3% and 94% respectively, and double throughput value was generated if compared to the proposed AES-128 design. Despite of these, the proposed AES-128 design increased the throughput by 22% and reduced the power consumed to 56% with 46.8% slices usage compared to the AES designs from previous studies. At hardware level, the proposed Blowfish design continued to be implemented and validated on ZedBoard and Zynq7000 AP SoC ZC702 FPGA platforms operated at 2.4 GHz ZigBee standard via XBee-PRO ZigBee through-hole XBP24CZ7PIT-004 for real-time data transmission. Two FPGA-based radio platforms were used as transmitter and receiver to form a two-way communication and measured in non-line-of-sight (NLOS) indoor environment based on point-to-point (P2P) topology within wireless personal area network (WPAN). The performance results indicated that the proposed P2M Blowfish radio system possessed a good quality in wireless data transmission with the bit-error-rate (BER) of 6.25x10-3, maximum signal strength of -34.58 dBm and maximum communication range of 61 m at 10 dBm transmitter radio frequency (RF) power level. The improvement in performance analysis either in the software or hardware level shown by the proposed P2M Blowfish has confirmed that this design has the ability to replace the existing AES scheme in mobile devices for the IoT application

VHDL Implementation of 128 bit Pipelined Blowfish Algorithm

Communication through public networks imposes threat to our sensitive data. Information security plays an important role in public networking and wireless communication. In order to achieve the protection of information or private data in networking, Cryptography can be used. It is the automated method in which security goals are accomplished. Cryptographic algorithm is a mathematical function used in Encryption and Decryption process. Blowfish is a keyed symmetric Cryptographic algorithm. It is a very fast and useful scheme for Encryption and Decryption. A key is the strongest point of any algorithm but it can become the weakest point if it is not secured. Our information can be secured if it is encrypted by using multiple keys. Hence implementation of Blowfish algorithm is very much use. Usually blowfish in existing method is 64 bit block cipher and Throughput depends on the size of the blocks applied. In this proposed paper, the blowfish algorithm is designed for 128 bit block size and pipelining operation is carried to improve the speed and reduce the delay accordingly, and so that this architecture improves the throughput of an encoder. The implementation results indicate that the proposed pipelined architecture shows 10% of improvement in Throughput. VHDL Implementation of proposed architecture has done by using XILINX ISE 9.1

Cryptoraptor : high throughput reconfigurable cryptographic processor for symmetric key encryption and cryptographic hash functions

textIn cryptographic processor design, the selection of functional primitives and connection structures between these primitives are extremely crucial to maximize throughput and flexibility. Hence, detailed analysis on the specifications and requirements of existing crypto-systems plays a crucial role in cryptographic processor design. This thesis provides the most comprehensive literature review that we are aware of on the widest range of existing cryptographic algorithms, their specifications, requirements, and hardware structures. In the light of this analysis, it also describes a high performance, low power, and highly flexible cryptographic processor, Cryptoraptor, that is designed to support both today's and tomorrow's encryption standards. To the best of our knowledge, the proposed cryptographic processor supports the widest range of cryptographic algorithms compared to other solutions in the literature and is the only crypto-specific processor targeting the future standards as well. Unlike previous work, we aim for maximum throughput for all known encryption standards, and to support future standards as well. Our 1GHz design achieves a peak throughput of 128Gbps for AES-128 which is competitive with ASIC designs and has 25X and 160X higher throughput per area than CPU and GPU solutions, respectively.Electrical and Computer Engineerin

An Overview of Parallel Symmetric Cipher of Messages

مقدمة: على الرغم من التطورات الهامة في الاتصالات والتكنولوجيا، فقد أثبتت حماية البيانات نفسها كواحدة من أكبر الاهتمامات. يجب تشفير البيانات من أجل الارتباط بشكل آمن وسريع من خلال نقل البيانات التكنولوجية على شبكة الإنترنت. يمكن تعريف عملية التشفير بانها تحويل النص العادي إلى نص مشفر لا يمكن قراءته أو تغييره بواسطة الأشخاص المؤذيين.            طرق العمل: من أجل الحفاظ على الدرجة المطلوبة من الأمان ، استغرقت كل من عمليات تحليل التشفير وفك التشفير وقتًا طويلاً. ومع ذلك, من أجل تقليل مقدار الوقت المطلوب لإكمال عمليات التشفير وفك التشفير، طبق العديد من الباحثين طريقة التشفير بطريقة موازية. لقد كشف البحث الذي تم إجراؤه حول المشكلة عن العديد من الإجابات المحتملة. استخدم الباحثون التوازي لتحسين إنتاجية خوارزمياتهم، مما سمح لهم بتحقيق مستويات أداء أعلى في خوارزمية التشفير.                             النتائج: أظهرت الأبحاث الحديثة حول تقنيات التشفير المتوازي أن وحدات معالجة الرسومات (GPUs) تعمل بشكل أفضل من الأنظمة الأساسية المتوازية الأخرى عند مقارنة مستويات أداء التشفير.   الاستنتاجات: لإجراء بحث مقارنة حول أهم خوارزميات التشفير المتوازية من حيث فعالية أمن البيانات وطول المفتاح والتكلفة والسرعة، من بين أمور أخرى. تستعرض هذه الورقة العديد من الخوارزميات المتوازية الهامة المستخدمة في تشفير البيانات وفك تشفيرها في جميع التخصصات. ومع ذلك، يجب النظر في معايير أخرى لإظهار مصداقية أي تشفير. تعتبر اختبارات العشوائية مهمة جدًا لاكتشافها وتم تسليط الضوء عليها في هذه الدراسة.                                                              Background: Despite significant developments in communications and technology, data protection has established itself as one of the biggest concerns. The data must be encrypted in order to link securely, quickly through web-based technological data transmission. Transforming plain text into ciphered text that cannot be read or changed by malicious people is the process of encryption. Materials and Methods: In order to maintain the required degree of security, both the cryptanalysis and decryption operations took a significant amount of time. However, in order to cut down on the amount of time required for the encryption and decryption operations to be completed, several researchers implemented the cryptography method in a parallel fashion. The research that has been done on the problem has uncovered several potential answers. Researchers used parallelism to improve the throughput of their algorithms, which allowed them to achieve higher performance levels on the encryption algorithm. Results: Recent research on parallel encryption techniques has shown that graphics processing units (GPUs) perform better than other parallel platforms when comparing their levels of encryption performance. Conclusion: To carry out comparison research on the most significant parallel crypto algorithms in terms of data security efficacy, key length, cost, and speed, among other things. This paper reviews various significant parallel algorithms used for data encryption and decryption in all disciplines. However, other criteria must be considered in order to show the trustworthiness of any encryption. Randomness tests are very important to discover and are highlighted in this study

High throughput FPGA Implementation of Data Encryption Standard with time variable sub-keys

The Data Encryption Standard (DES) was the first modern and the most popular symmetric key algorithm used for encryption and decryption of digital data. Even though it is nowadays not considered secure against a determined attacker, it is still used in legacy applications. This paper presents a secure and high-throughput Field Programming Gate Arrays (FPGA) implementation of the Data Encryption Standard algorithm. This is achieved by combining 16 pipelining concept with time variable sub-keys and compared with previous illustrated encryption algorithms. The sub-keys vary over time by changing the key schedule permutation choice 1. Therefore, every time the plaintexts are encrypted by different sub-keys. The proposed algorithm is implemented on Xilinx Spartan-3e (XC3s500e) FPGA. Our DES design achieved a data encryption rate of 10305.95 Mbit/s and 2625 number of occupied CLB slices. These results showed that the proposed implementation is one of the fastest hardware implementations with much greater security

Cryptarray A Scalable And Reconfigurable Architecture For Cryptographic Applications

Cryptography is increasingly viewed as a critical technology to fulfill the requirements of security and authentication for information exchange between Internet applications. However, software implementations of cryptographic applications are unable to support the quality of service from a bandwidth perspective required by most Internet applications. As a result, various hardware implementations, from Application-Specific Integrated Circuits (ASICs), Field-Programmable Gate Arrays (FPGAs), to programmable processors, were proposed to improve this inadequate quality of service. Although these implementations provide performances that are considered better than those produced by software implementations, they still fall short of addressing the bandwidth requirements of most cryptographic applications in the context of the Internet for two major reasons: (i) The majority of these architectures sacrifice flexibility for performance in order to reach the performance level needed for cryptographic applications. This lack of flexibility can be detrimental considering that cryptographic standards and algorithms are still evolving. (ii) These architectures do not consider the consequences of technology scaling in general, and particularly interconnect related problems. As a result, this thesis proposes an architecture that attempts to address the requirements of cryptographic applications by overcoming the obstacles described in (i) and (ii). To this end, we propose a new reconfigurable, two-dimensional, scalable architecture, called CRYPTARRAY, in which bus-based communication is replaced by distributed shared memory communication. At the physical level, the length of the wires will be kept to a minimum. CRYPTARRAY is organized as a chessboard in which the dark and light squares represent Processing Elements (PE) and memory blocks respectively. The granularity and resource composition of the PEs is specifically designed to support the computing operations encountered in cryptographic algorithms in general, and symmetric algorithms in particular. Communication can occur only between neighboring PEs through locally shared memory blocks. Because of the chessboard layout, the architecture can be reconfigured to allow computation to proceed as a pipelined wave in any direction. This organization offers a high computational density in terms of datapath resources and a large number of distributed storage resources that easily support a high degree of parallelism and pipelining. Experimental prototyping a small array on FPGA chips shows that this architecture can run at 80.9 MHz producing 26,968,716 outputs every second in static reconfiguration mode and 20,226,537 outputs every second in dynamic reconfiguration mode

Autotuning the Intel HLS Compiler using the Opentuner Framework

High level synthesis (HLS) tools can be used to improve design flow and decrease verification times for field programmable gate array (FPGA) and application specific integrated circuit (ASIC) design. The Intel HLS Compiler is a high level synthesis tool that takes in untimed C/C++ as input and generates production-quality register transfer level (RTL) code that is optimized for Intel FPGAs. The translation does, however, require multiple iterations and manual optimizations to get comparable synthesized results to that of a solution written in a hardware descriptive language. The synthesis results can vary greatly based upon coding style and optimization techniques, and typically require an in-depth knowledge of FPGAs to fully optimize the translation which limits the audience of the tool. The extra abstraction that the C/C++ source code presents can also make it difficult to meet more specific design requirements; this includes designs to meet specific resource usage or performance based metrics. To improve the quality of results generated by the Intel HLS Compiler without a manual iterative process that requires an in-depth knowledge of FPGAs, this research proposes a method of automating some of the optimization techniques that improve the synthesized design through an autotuning process. The proposed approach utilizes the PyCParser library to parse C source files and the OpenTuner Framework to autotune the synthesis to provide a method that generates results that better meet the needs of the designer's requirements through lower FPGA resource usage or increased design performance. Such functionality is not currently available in Intel's commercial tools. The proposed approach was tested with the CHStone Benchmarking Suite of C programs as well as a standard digital signal processing finite impulse response filter. The results show that the commercial HLS tool can be automatically autotuned through placeholder injection using a source parsing tool for C code and using the OpenTuner Framework to autotune the results. For designs that are small in nature and include conducive structures to be autotuned, the results indicate resource usage reductions and/or performance increases of up to 40% as compared to the default Intel HLS Compiler results. The method developed in this research also allows additional design targets to be specified through the autotuner for consideration in the synthesized design which can yield results that are better matched to a design's requirements

Comparison of Hand-Written RTL code against High-Level Synthesis for Blowfish and Tiny Encrpytion Algorithm (TEA)

Cryptography is the backbone of a secure and reliable communication system. Data security while transmission depends upon the strength of cryptographic algorithm. In this work, Tiny Encryption Algorithms (TEA) and Blowfish algorithms has been implemented using the High Level Synthesis (HLS) and hand-written Register Transfer Level (RTL) approaches in Xilinx Vivado HLS and Xilinx ISE. Comparative evaluation for both implementation approaches has shown that RTL approach is outperforming HLS approach in both algorithms for different parameters like throughput, frequency etc., due to flexibility of designing modules in RTL as compared to HLS approach