Implementation of Compressive Sensing Algorithms on Arm Cortex Processor and FPGAs

Nowadays, communication systems require huge amounts of data to be processed. Some examples of these systems include radar systems, video streaming, and many other multimedia applications. These systems require large amounts of bandwidth to satisfy the Nyquist rate. Compressive Sensing is proposed as a way to reduce their bandwidth requirements. Compressive Sensing algorithms are generally implemented at the receiver to reconstruct the original signal from a reduced set of samples. This methodology eliminates data which is relatively insignificant. It possesses the potential to eliminate the use of large bandwidth, cost effective matched filters, and high-frequency analog-todigital converters at the receiver in the case of radar systems. Compressive Sensing is widely used in areas such as Digital Image Processing, Digital Signal Processing, Radars, and Wireless Sensor Networks. This research investigates on three main optimization techniques commonly used in Compressive Sensing: Optimal Matching Pursuit (OMP), Compressive Sampling Matching Pursuit (CSMP) and Stagewise Orthogonal Matching Pursuit (StOMP). These algorithms were implemented and tested on an ARM processor, and on a Field Programmable Gate Array (FPGA). During the first stage of this research, the optimization techniques were implemented in MATLAB. In the second stage, they were implemented on an ARM processor to accelerate their performance. The algorithms show a considerable acceleration on the ARM processor compared to MATLAB. In the final stage of the research, linear algebra operations were implemented on an FPGA to further accelerate their performance. The results show further improvement when part of the code was implemented on an FPGA

Turbo Bayesian Compressed Sensing

Compressed sensing (CS) theory specifies a new signal acquisition approach, potentially allowing the acquisition of signals at a much lower data rate than the Nyquist sampling rate. In CS, the signal is not directly acquired but reconstructed from a few measurements. One of the key problems in CS is how to recover the original signal from measurements in the presence of noise. This dissertation addresses signal reconstruction problems in CS. First, a feedback structure and signal recovery algorithm, orthogonal pruning pursuit (OPP), is proposed to exploit the prior knowledge to reconstruct the signal in the noise-free situation. To handle the noise, a noise-aware signal reconstruction algorithm based on Bayesian Compressed Sensing (BCS) is developed. Moreover, a novel Turbo Bayesian Compressed Sensing (TBCS) algorithm is developed for joint signal reconstruction by exploiting both spatial and temporal redundancy. Then, the TBCS algorithm is applied to a UWB positioning system for achieving mm-accuracy with low sampling rate ADCs. Finally, hardware implementation of BCS signal reconstruction on FPGAs and GPUs is investigated. Implementation on GPUs and FPGAs of parallel Cholesky decomposition, which is a key component of BCS, is explored. Simulation results on software and hardware have demonstrated that OPP and TBCS outperform previous approaches, with UWB positioning accuracy improved by 12.8x. The accelerated computation helps enable real-time application of this work

Design issues and challenges of an FPGA-based orthogonal matching pursuit implementation for compressive sensing reconstruction

Compressive sensing (CS) is as an evolving research area in signal processing due to the advantages offered for signal compression. Based on the sparsity of signals, CS allows the sampling of sparse signals under the sub-Nyquist rate, and yet promises a reliable data recovery. To date, the implementation of practical applications of CS in hardware platforms, especially in real-time applications, still faces challenging issues due to the high computational complexity of its algorithms, hence leading to high power-consuming processes. There are several CS reconstruction approaches, and orthogonal matching pursuit (OMP) is one of the best and popular algorithms implemented. However, this algorithm faces two (2) major process issues: optimisation and the least square problem. Due to OMP’s significant contribution, this paper presents an overview of the design issues and challenges of OMP algorithm implementation for CS reconstruction. The fieldprogrammable gate array (FPGA) as a viable hardware solution for OMP implementation is reviewed and discussed based on reconstruction time, signal size, number of measurements, sparsity and features

HDL Implementation of OMP Based Compressed Sampled Reconstruction Algorithm

Nearly all signal acquisition techniques follow the much celebrated Shannon’s sampling theorem which specifies that the sampling rate of the signal must be at least two times the highest frequency present in the signal. The sampled data is then compressed to make it efficient for storage and transmission. Conventional approach to sampling is expensive in terms of data storage and transmission due to the large number of samples generated. Some cases increasing sampling rate is also very expensive like high speed ADCs, imaging systems, etc. It is also inefficient since lot of the data produced is redundant in nature since most naturally occurring signals are sparse in nature. Compressive sensing addresses these inefficiencies by directly acquiring a compressed signal representation without going through the intermediate stage of acquiring all samples. The sampled data can be reconstructed using computationally intensive algorithm. CS is also superior to conventional approaches in the following regard that the CS performs the time consuming processes at the recovery end rather than the sensing end. Reconstruction algorithms are complex and implementation of these algorithms in software is extremely slow and power consuming due to the reason that it is based on several layer of abstraction and shared resources between multiple processes. On the other hand hardware implementation takes advantage of hardware parallelism, custom datapath creation ability and dedicated hardware for each task. The hardware implementation in the project will be utilizing the OMP algorithm due to its less complexity and faster solution time. The algorithm will be implemented using VHDL. The objective of the project will be to implement the OMP algorithm using optimal resources so as to reduce the reconstruction time without compromising with accuracy intended

FPGA Implementation of Real-Time Compressive Sensing with Partial Fourier Dictionary

This paper presents a novel real-time compressive sensing (CS) reconstruction which employs high density field-programmable gate array (FPGA) for hardware acceleration. Traditionally, CS can be implemented using a high-level computer language in a personal computer (PC) or multicore platforms, such as graphics processing units (GPUs) and Digital Signal Processors (DSPs). However, reconstruction algorithms are computing demanding and software implementation of these algorithms is extremely slow and power consuming. In this paper, the orthogonal matching pursuit (OMP) algorithm is refined to solve the sparse decomposition optimization for partial Fourier dictionary, which is always adopted in radar imaging and detection application. OMP reconstruction can be divided into two main stages: optimization which finds the closely correlated vectors and least square problem. For large scale dictionary, the implementation of correlation is time consuming since it often requires a large number of matrix multiplications. Also solving the least square problem always needs a scalable matrix decomposition operation. To solve these problems efficiently, the correlation optimization is implemented by fast Fourier transform (FFT) and the large scale least square problem is implemented by Conjugate Gradient (CG) technique, respectively. The proposed method is verified by FPGA (Xilinx Virtex-7 XC7VX690T) realization, revealing its effectiveness in real-time applications

Parallelisation of greedy algorithms for compressive sensing reconstruction

Compressive Sensing (CS) is a technique which allows a signal to be compressed at the same time as it is captured. The process of capturing and simultaneously compressing the signal is represented as linear sampling, which can encompass a variety of physical processes or signal processing. Instead of explicitly identifying redundancies in the source signal, CS relies on the property of sparsity in order to reconstruct the compressed signal. While linear sampling is much less burdensome than conventional compression, this is more than made up for by the high computational cost of reconstructing a signal which has been captured using CS. Even when using some of the fastest reconstruction techniques, known as greedy pursuits, reconstruction of large problems can pose a significant burden, consuming a great deal of memory as well as compute time. Parallel computing is the foundation of the field of High Performance Computing (HPC). Modern supercomputers are generally composed of large clusters of standard servers, with a dedicated low-latency high-bandwidth interconnect network. On such a cluster, an appropriately written program can harness vast quantities of memory and computational power. However, in order to exploit a parallel compute resource, an algorithm usually has to be redesigned from the ground up. In this thesis I describe the development of parallel variants of two algorithms commonly used in CS reconstruction, Matching Pursuit (MP) and Orthogonal Matching Pursuit (OMP), resulting in the new distributed compute algorithms DistMP and DistOMP. I present the results from experiments showing how DistMP and DistOMP can utilise a compute cluster to solve CS problems much more quickly than a single computer could alone. Speed-up of as much as a factor of 76 is observed with DistMP when utilising 210 workers across 14 servers, compared to a single worker. Finally, I demonstrate how DistOMP can solve a problem with a 429GB equivalent sampling matrix in as little as 62 minutes using a 16-node compute cluster.Funded by an ICASE award from the Engineering and Physical Sciences Research Council, with sponsorship provided by Thales Research and Technology

Efficient detection for multifrequency dynamic phasor analysis

Analysis of harmonic and interharmonic phasors is a promising smart grid measurement and diagnostic tool. This creates the need to deal with multiple phasor components having different amplitudes, including interharmonics with unknown frequency locations. The Compressive Sensing Taylor-Fourier Multifrequency (CSTFM) algorithm provides very accurate results under demanding test conditions, but is computationally demanding. In this paper we present a novel frequency search criterion with significantly improved effectiveness, resulting in a very efficient revised CSTFM algorithm

MFPA: Mixed-Signal Field Programmable Array for Energy-Aware Compressive Signal Processing

Compressive Sensing (CS) is a signal processing technique which reduces the number of samples taken per frame to decrease energy, storage, and data transmission overheads, as well as reducing time taken for data acquisition in time-critical applications. The tradeoff in such an approach is increased complexity of signal reconstruction. While several algorithms have been developed for CS signal reconstruction, hardware implementation of these algorithms is still an area of active research. Prior work has sought to utilize parallelism available in reconstruction algorithms to minimize hardware overheads; however, such approaches are limited by the underlying limitations in CMOS technology. Herein, the MFPA (Mixed-signal Field Programmable Array) approach is presented as a hybrid spin-CMOS reconfigurable fabric specifically designed for implementation of CS data sampling and signal reconstruction. The resulting fabric consists of 1) slice-organized analog blocks providing amplifiers, transistors, capacitors, and Magnetic Tunnel Junctions (MTJs) which are configurable to achieving square/square root operations required for calculating vector norms, 2) digital functional blocks which feature 6-input clockless lookup tables for computation of matrix inverse, and 3) an MRAM-based nonvolatile crossbar array for carrying out low-energy matrix-vector multiplication operations. The various functional blocks are connected via a global interconnect and spin-based analog-to-digital converters. Simulation results demonstrate significant energy and area benefits compared to equivalent CMOS digital implementations for each of the functional blocks used: this includes an 80% reduction in energy and 97% reduction in transistor count for the nonvolatile crossbar array, 80% standby power reduction and 25% reduced area footprint for the clockless lookup tables, and roughly 97% reduction in transistor count for a multiplier built using components from the analog blocks. Moreover, the proposed fabric yields 77% energy reduction compared to CMOS when used to implement CS reconstruction, in addition to latency improvements