8 research outputs found

    Sierra County Advocate, 1889-01-19

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    https://digitalrepository.unm.edu/sc_advocate_news/2260/thumbnail.jp

    Just-in-time Hardware generation for abstracted reconfigurable computing

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    This thesis addresses the use of reconfigurable hardware in computing platforms, in order to harness the performance benefits of dedicated hardware whilst maintaining the flexibility associated with software. Although the reconfigurable computing concept is not new, the low level nature of the supporting tools normally used, together with the consequent limited level of abstraction and resultant lack of backwards compatibility, has prevented the widespread adoption of this technology. In addition, bandwidth and architectural limitations, have seriously constrained the potential improvements in performance. A review of existing approaches and tools flows is conducted to highlight the current problems being faced in this field. The objective of the work presented in this thesis is to introduce a radically new approach to reconfigurable computing tool flows. The runtime based tool flow introduces complete abstraction between the application developer and the underlying hardware. This new technique eliminates the ease of use and backwards compatibility issues that have plagued the reconfigurable computing concept, and could pave the way for viable mainstream reconfigurable computing platforms. An easy to use, cycle accurate behavioural modelling system is also presented, which was used extensively during the early exploration of new concepts and architectures. Some performance improvements produced by the new reconfigurable computing tool flow, when applied to both a MIPS based embedded platform, and the Cray XDl, are also presented. These results are then analyzed and the hardware and software factors affecting the performance increases that were obtained are discussed, together with potential techniques that could be used to further increase the performance of the system. Lastly a heterogenous computing concept is proposed, in which, a computer system, containing multiple types of computational resource is envisaged, each having their own strengths and weaknesses (e.g. DSPs, CPUs, FPGAs). A revolutionary new method of fully exploiting the potential of such a system, whilst maintaining scalability, backwards compatibility, and ease of use is also presented

    Reconfiguration of field programmable logic in embedded systems

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    1871-03-22

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    The Old Commonwealth was a weekly newspaper published in Harrisonburg, Va., between 1865 and 1884

    Algoritmos para alocação de recursos em arquiteturas reconfiguraveis

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    Orientador: Guido Costa Souza de AraujoTese (doutorado) - Universidade Estadual de Campinas, Instituto de ComputaçãoResumo: Pesquisas recentes na área de arquiteturas reconfiguráveis mostram que elas oferecem um desempenho melhor que os processadores de propósito geral (GPPs - General Purpose Processors), aliado a uma maior flexibilidade que os ASICs (Application Specific Integrated Circuits). Uma mesma arquitetura recongurável pode ser adaptada para implementar aplicações diferentes, permitindo a especialização do hardware de acordo com a demanda computacional da aplicação. Neste trabalho, nos estudamos o projeto de sistemas dedicados baseado em uma arquitetura reconfigurável. Adotamos a abordagem de extensão do conjunto de instruções, na qual o conjunto de instruções de um GPP e acrescido de instruções especializadas para uma aplicação. Estas instruções correspondem a trechos da aplicação e são executadas em um datapath dinamicamente recongurável, adicionado ao hardware do GPP. O tema central desta tese e o problema de compartilhamento de recursos no projeto do datapath reconfigurável. Dado que os trechos da aplicação são modelados como grafos de luxo de dados e controle (Control/Data-Flow Graphs ¿ CDFGs), o problema de combinação de CDFGs consiste em projetar um datapath reconfigurável com área mínima. Nos apresentamos uma demonstração de que este problema e NP-completo. Nossas principais contribuições são dois algoritmos heurísticos para o problema de combinação de CDFGs. O primeiro tem o objetivo de minimizar a área das interconexões do datapath reconfigurável, enquanto que o segundo visa a minimização da área total. Avaliações experimentais mostram que nossa primeira heurística resultou em uma redução media de 26,2% na área das interconexões, em relação ao método mais utilizado na literatura. O erro máximo de nossas soluções foi em media 4,1% e algumas soluções ótimas foram obtidas. Nosso segundo algoritmo teve tempos de execução comparáveis ao método mais rápido conhecido, obtendo uma redução media de 20% na área. Em relação ao melhor método para área conhecido, nossa heurística produziu áreas um pouco menores, alcançando um speed up médio de 2500. O algoritmo proposto também produziu áreas menores, quando comparado a uma ferramenta de síntese comercialAbstract: Recent work in reconfigurable architectures shows that they ofter a better performance than general purpose processors (GPPs), while offering more exibility than ASICs (Application Specific Integrated Circuits). A reconfigurable architecture can be adapted to implement different applications, thus allowing the specialization of the hardware according to the computational demands. In this work we describe an embedded systems project based on a reconfigurable architecture. We adopt an instruction set extension technique, where specialized instructions for an application are included into the instruction set of a GPP. These instructions correspond to sections of the application, and are executed in a dynamically reconfigurable datapath, added to the GPP's hardware. The central focus of this theses is the resource sharing problem in the design of reconfigurable datapaths. Since the application sections are modeled as control/data-ow graphs (CDFGs), the CDFG merging problem consists in designing a reconfigurable datapath with minimum area. We prove that this problem is NP-complete. Our main contributions are two heuristic algorithms to the CDFG merging problem. The first has the goal of minimizing the reconfigurable datapath interconnection area, while the second minimizes its total area. Experimental evaluation showed that our first heuristic produced an average 26.2% area reduction, with respect to the most used method. The maximum error of our solutions was on average 4.1%, and some optimal solutions were found. Our second algorithm approached, in execution times, the fastest previous solution, and produced datapaths with an average area reduction of 20%. When compared to the best known area solution, our approach produced slightly better areas, while achieving an average speedup of 2500. The proposed algorithm also produced smaller areas, when compared to an industry synthesis toolDoutoradoDoutor em Ciência da Computaçã

    Analysis of the modifying influence of Plastin 3 (PLS3) on Spinal Muscular Atrophy (SMA) by generation of transgenic mouse models

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    Spinal muscular atrophy (SMA) is a neurodegenerative disease characterized by the loss of α-motor neurons in the ventral horn of the spinal cord. Depending on the severity, the clinical spectrum of SMA ranges from early infant death to normal adult life with only mild muscle weakness. To date, no cure is available. SMA is caused by the homozygous loss of the survival motor neuron gene 1 (SMN1). Besides SMN1, another nearly identical copy of the gene is present in the human genome, thus called SMN2. In the SMN2 gene, a C to T transition in exon 7 leads to the disruption of an exonic splicing enhancer, resulting in alternative splicing of SMN2 pre-mRNA and skipping of exon 7 in 90 % of total transcript. However, about 10 % of full length (FL) transcripts are still being produced by SMN2. Through gene duplication events, SMN2 is present in varying copy numbers in the human population, ranging from the total absence to a maximum of 4 SMN2 copies per allele. Since every copy produces about 10 % FL transcript, SMA severity is inversely correlated with SMN2 copy number. For a long time, SMN2 was the only known modifying gene and has therefore been target for the development of therapeutic strategies. The observation of SMN1-deleted patients with either extremely weakened or even absent symptoms in the presence of only a small number of SMN2 copies has in the past been associated with the existence of SMA-modifying genes. Finally, in 2008 the Actin-bundling protein Plastin 3 (PLS3) has been identified as a protective modifying gene showing high expression in asymptomatic homozygously SMN1- deleted siblings of discordant SMA families in our group (Oprea et al., 2008). Cell culture as well as in vivo experiments in a zebrafish SMA model revealed that PLS3 overexpression rescues the axonal outgrowth phenotype. The goal of the present study was to address the question whether PLS3 overexpression is able to rescue the phenotype in an existing SMA mouse model. Furthermore, it was asked which effect PLS3 overexpression has on the development of neuromuscular junctions (NMJ) as well as muscle development and function. Using the Cre/loxP system, transgenic mice were generated expressing a V5-tagged version of human PLS3 (PLS3V5) either ubiquitously or motor neuron specifically (Hb9 promoter). In a next step, PLS3V5 transgenic mice were crossed onto the SMA background using the Hung mouse model. All mice were crossed congenic onto clean C57BL/6N background to exclude any background modifying effects. Transgenic PLS3V5 mice on wildtype (wt) as well as on SMA background were histologically (Motor neurons, NMJs, muscle) and functionally (Motoric tests, weight, survival) analyzed in detail. Ubiquitous as well as motor neuron specific PLS3V5 expression was proven by qRT-PCR, Western blot analysis and immunohistochemistry. PLS3V5 transgenic mice on wt as well as on SMA background showed remarkable influence of PLS3 overexpression on motor neuron and NMJ phenotype: The motor neuron and Acetylcholine receptor (AChR) cluster size was highly increased as compared to wt or SMA littermates. Time course measurements of presynaptic sprouting during the process of axonal pruning revealed highly improved axonal connectivity. These findings raised the question whether the increase of AChR cluster size in transgenic animals is an effect of pre- or postsynaptic PLS3V5 overexpression. To address this issue, motor neuron specific PLS3V5 overexpression was analyzed in wt mice. Strikingly, motor neuron specific overexpression of PLS3V5 was sufficient to increase AChR cluster and muscle fiber size, further strengthening the positive impact of neuronal PLS3V5 expression on neurotransmission. Moreover, electrophysiological analyzes (NMJ quantal content measurements, Motor Unit Number Estimate (MUNE)) will be performed in the future and correlated with the recent findings. Despite this positive impact on axon biology, PLS3 overexpression neither increased survival nor improved motoric ability in the severe type I-like SMA mouse model used in this study. Therefore, it was hypothesized that a certain amount of SMN is required – similar to asymptomatic humans, who own at least 3 SMN2 copies – to rescue the SMA phenotype. To test this hypothesis, the PLS3V5 transgene is currently crossed onto a milder SMA background. Additionally, PLS3V5 was up to now only heterozygously overexpressed in SMA mice. Since also higher PLS3V5 levels might be necessary to finally improve SMA symptoms, PLS3V5 will be homozygously expressed in the SMA background in the future

    The Palmetto Standard- April 7, 1852

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    The collection consists of issues of the Palmetto Standard a weekly newspaper printed in Chester, S.C. from 1851 through 1853 before changing its name to the Chester Standard in 1854.This issue, scanned from microfilm, is from April 7, 1852 (volume III, number 14).https://digitalcommons.winthrop.edu/palmettostandard/1015/thumbnail.jp
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