Discrimination of surface and volume states in fully depleted field-effect devices on thick insulator substrates

The behavior of electronic devices fabricated on thin, lightly doped semiconductor layers can be significantly influenced by very low levels of non-ideal charge states. Such devices typically operate in a fully depleted mode, and can exhibit significantly different electrical properties and characteristics than their bulk material counterparts. Traditional interpretation of device characteristics may identify the existence of such non-idealities, but fail to ascertain if the origin is from within the semiconductor layer or associated with the interfaces to adjacent dielectric materials. This leads to ambiguity in how to rectify the behavior and improve device performance. Characterizing non-idealities through electrical means requires adaptations in both measurement techniques and data interpretation. Some of these adaptations have been applied in material systems like silicon-on-insulator (SOI), however in systems where the semiconductor film becomes increasingly isolated on very thick insulators (i.e., glass), the device physics of operation presents new challenges. Overcoming the obstacles in interpretation can directly aid the technology development of thin semiconductor films on thick insulator substrates. The investigation is initiated by isolating the interface of crystalline silicon bonded to a thick boro-aluminosilicate glass insulator. The interface is studied through traditional bulk capacitance-voltage (C-V) methods, and the electrical fragility of the interface is exposed. This reveals the necessity to discriminate between interface states and bulk defect states. To study methods of discrimination, the physics of field-effect devices fabricated on isolated semiconducting films is explained. These devices operate in a fully depleted state; expressions that describe the C-V relationship with a single gate electrode are derived and explored. The discussion presents an explanation of how surface and volume charge states each contribute to the C-V characteristic behavior. Application of this adapted C-V theory is then applied to the gated-diode, a novel device which has proven to be instrumental in charge state discrimination. Through this adaptation, the gated-diode is used to extract recombination-generation parameters isolated to the top surface, bottom surface and within the volume of the film. The methodology is developed through an exploration of devices fabricated on SOI and silicon-on-glass (SiOG) substrates, and furthers the understanding needed to improve material quality and device performance

Novel Processing and Electrical Characterization of Nanowires

This thesis investigates novel electrical nanowire characterization tools and devices. Conventional characterization methods, long available to bulk semiconductor samples, have been adapted and transferred to the nanowire geometry. The first part of the thesis describes the development of Hall effect measurements, an entirely new characterization tool for nanowires. It is shown that Hall effect measurements can be performed on InP core-shell nanowires using a self-aligned lifting layer. By combining experimental data with results from simulations of band diagrams and current distribution under the influence of a magnetic field, the carrier density in the n-type nanowire shell can be determined. We found that the nanowire shell exhibits a doping gradient along the length of the nanowire. This doping inhomogeneity is important to account for and engineer when making devices using InP nanowires. The second part of the thesis demonstrates how capacitance-voltage measurements can be performed on arrays of InAs nanowires. Using a novel device structure, the capacitance signal from the nanowires can be distinguished from parasitic capacitances. A model was developed to simulate the capacitance-voltage behavior of the nanowires and was fitted to the experimental data to extract the doping concentration. Furthermore, the hysteresis observed in the capacitance-voltage sweeps was used to calculate the trap density close to the InAs-HfO2 dielectric interface. Finally, studies of gate effects in nanowires are presented. We demonstrate how the gating efficiency is improved by means of wrapped or semiwrapped gates on nanowires. Field-effect transistors made from InP nanowires are described that exhibit both ambipolar behavior and gating efficiency only 13% lower than the theoretical limit. These properties were used to fabricate a field-effect diode, a device in which a p-n junction is formed without any doping incorporation in the active region. We also demonstrate how nanowires positioned laterally on a substrate can be equipped with a fully wrapped gate electrode. This device was developed as part of a platform to perform basic research in which a uniform gating effect is desired

Feature Papers in Electronic Materials Section

This book entitled "Feature Papers in Electronic Materials Section" is a collection of selected papers recently published on the journal Materials, focusing on the latest advances in electronic materials and devices in different fields (e.g., power- and high-frequency electronics, optoelectronic devices, detectors, etc.). In the first part of the book, many articles are dedicated to wide band gap semiconductors (e.g., SiC, GaN, Ga2O3, diamond), focusing on the current relevant materials and devices technology issues. The second part of the book is a miscellaneous of other electronics materials for various applications, including two-dimensional materials for optoelectronic and high-frequency devices. Finally, some recent advances in materials and flexible sensors for bioelectronics and medical applications are presented at the end of the book

Miniaturized Transistors

What is the future of CMOS? Sustaining increased transistor densities along the path of Moore's Law has become increasingly challenging with limited power budgets, interconnect bandwidths, and fabrication capabilities. In the last decade alone, transistors have undergone significant design makeovers; from planar transistors of ten years ago, technological advancements have accelerated to today's FinFETs, which hardly resemble their bulky ancestors. FinFETs could potentially take us to the 5-nm node, but what comes after it? From gate-all-around devices to single electron transistors and two-dimensional semiconductors, a torrent of research is being carried out in order to design the next transistor generation, engineer the optimal materials, improve the fabrication technology, and properly model future devices. We invite insight from investigators and scientists in the field to showcase their work in this Special Issue with research papers, short communications, and review articles that focus on trends in micro- and nanotechnology from fundamental research to applications

Miniaturized Transistors, Volume II

In this book, we aim to address the ever-advancing progress in microelectronic device scaling. Complementary Metal-Oxide-Semiconductor (CMOS) devices continue to endure miniaturization, irrespective of the seeming physical limitations, helped by advancing fabrication techniques. We observe that miniaturization does not always refer to the latest technology node for digital transistors. Rather, by applying novel materials and device geometries, a significant reduction in the size of microelectronic devices for a broad set of applications can be achieved. The achievements made in the scaling of devices for applications beyond digital logic (e.g., high power, optoelectronics, and sensors) are taking the forefront in microelectronic miniaturization. Furthermore, all these achievements are assisted by improvements in the simulation and modeling of the involved materials and device structures. In particular, process and device technology computer-aided design (TCAD) has become indispensable in the design cycle of novel devices and technologies. It is our sincere hope that the results provided in this Special Issue prove useful to scientists and engineers who find themselves at the forefront of this rapidly evolving and broadening field. Now, more than ever, it is essential to look for solutions to find the next disrupting technologies which will allow for transistor miniaturization well beyond silicon’s physical limits and the current state-of-the-art. This requires a broad attack, including studies of novel and innovative designs as well as emerging materials which are becoming more application-specific than ever before

FABRICATION AND CHARACTERIZATION OF ACTIVE NANOSTRUCTURES

Three different nanostructure active devices have been designed, fabricated and characterized. Junctionless transistors based on highly-doped silicon nanowires fabricated using a bottom-up fabrication approach are first discussed. The fabrication avoids the ion implantation step since silicon nanowires are doped in-situ during growth. Germanium junctionless transistors fabricated with a top down approach starting from a germanium on insulator substrate and using a gate stack of high-k dielectrics and GeO2 are also presented. The levels and origin of low-frequency noise in junctionless transistor devices fabricated from silicon nanowires and also from GeOI devices are reported. Low-frequency noise is an indicator of the quality of the material, hence its characterization can reveal the quality and perhaps reliability of fabricated transistors. A novel method based on low-frequency noise measurement to envisage trap density in the semiconductor bandgap near the semiconductor/oxide interface of nanoscale silicon junctionless transistors (JLTs) is presented. Low-frequency noise characterization of JLTs biased in saturation is conducted at different gate biases. The noise spectrum indicates either a Lorentzian or 1/f. A simple analysis of the low-frequency noise data leads to the density of traps and their energy within the semiconductor bandgap. The level of noise in silicon JLT devices is lower than reported values on transistors fabricated using a top-down approach. This noise level can be significantly improved by improving the quality of dielectric and the channel interface

Product assurance technology for procuring reliable, radiation-hard, custom LSI/VLSI electronics

Advanced measurement methods using microelectronic test chips are described. These chips are intended to be used in acquiring the data needed to qualify Application Specific Integrated Circuits (ASIC's) for space use. Efforts were focused on developing the technology for obtaining custom IC's from CMOS/bulk silicon foundries. A series of test chips were developed: a parametric test strip, a fault chip, a set of reliability chips, and the CRRES (Combined Release and Radiation Effects Satellite) chip, a test circuit for monitoring space radiation effects. The technical accomplishments of the effort include: (1) development of a fault chip that contains a set of test structures used to evaluate the density of various process-induced defects; (2) development of new test structures and testing techniques for measuring gate-oxide capacitance, gate-overlap capacitance, and propagation delay; (3) development of a set of reliability chips that are used to evaluate failure mechanisms in CMOS/bulk: interconnect and contact electromigration and time-dependent dielectric breakdown; (4) development of MOSFET parameter extraction procedures for evaluating subthreshold characteristics; (5) evaluation of test chips and test strips on the second CRRES wafer run; (6) two dedicated fabrication runs for the CRRES chip flight parts; and (7) publication of two papers: one on the split-cross bridge resistor and another on asymmetrical SRAM (static random access memory) cells for single-event upset analysis

GaN-based power devices: Physics, reliability, and perspectives

Over the last decade, gallium nitride (GaN) has emerged as an excellent material for the fabrication of power devices. Among the semicon- ductors for which power devices are already available in the market, GaN has the widest energy gap, the largest critical field, and the highest saturation velocity, thus representing an excellent material for the fabrication of high-speed/high-voltage components. The presence of spon- taneous and piezoelectric polarization allows us to create a two-dimensional electron gas, with high mobility and large channel density, in the absence of any doping, thanks to the use of AlGaN/GaN heterostructures. This contributes to minimize resistive losses; at the same time, for GaN transistors, switching losses are very low, thanks to the small parasitic capacitances and switching charges. Device scaling and monolithic integration enable a high-frequency operation, with consequent advantages in terms of miniaturization. For high power/high- voltage operation, vertical device architectures are being proposed and investigated, and three-dimensional structures—fin-shaped, trench- structured, nanowire-based—are demonstrating great potential. Contrary to Si, GaN is a relatively young material: trapping and degradation processes must be understood and described in detail, with the aim of optimizing device stability and reliability. This Tutorial describes the physics, technology, and reliability of GaN-based power devices: in the first part of the article, starting from a discussion of the main proper- ties of the material, the characteristics of lateral and vertical GaN transistors are discussed in detail to provide guidance in this complex and interesting field. The second part of the paper focuses on trapping and reliability aspects: the physical origin of traps in GaN and the main degradation mechanisms are discussed in detail. The wide set of referenced papers and the insight into the most relevant aspects gives the reader a comprehensive overview on the present and next-generation GaN electronics