Trojans in Early Design Steps—An Emerging Threat

Hardware Trojans inserted by malicious foundries during integrated circuit manufacturing have received substantial attention in recent years. In this paper, we focus on a different type of hardware Trojan threats: attacks in the early steps of design process. We show that third-party intellectual property cores and CAD tools constitute realistic attack surfaces and that even system specification can be targeted by adversaries. We discuss the devastating damage potential of such attacks, the applicable countermeasures against them and their deficiencies

PARISROC, a Photomultiplier Array Integrated Read Out Chip

PARISROC is a complete read out chip, in AMS SiGe 0.35 !m technology, for photomultipliers array. It allows triggerless acquisition for next generation neutrino experiments and it belongs to an R&D program funded by the French national agency for research (ANR) called PMm2: ?Innovative electronics for photodetectors array used in High Energy Physics and Astroparticles? (ref.ANR-06-BLAN-0186). The ASIC (Application Specific Integrated Circuit) integrates 16 independent and auto triggered channels with variable gain and provides charge and time measurement by a Wilkinson ADC (Analog to Digital Converter) and a 24-bit Counter. The charge measurement should be performed from 1 up to 300 photo- electrons (p.e.) with a good linearity. The time measurement allowed to a coarse time with a 24-bit counter at 10 MHz and a fine time on a 100ns ramp to achieve a resolution of 1 ns. The ASIC sends out only the relevant data through network cables to the central data storage. This paper describes the front-end electronics ASIC called PARISROC.Comment: IEEE Nuclear Science Symposium an Medical Imaging Conference (2009 NSS/MIC

A survey of behavioral-level partitioning systems

Many approaches have been developed to partition a system's behavioral description before a structural implementation is synthesized. We highlight the foundations and motivations for behavioral partitioning. We survey behavioral partitioning approaches, discussing abstraction levels, goals, major steps, and key assumptions in each

A 128K-bit CCD buffer memory system

A prototype system was implemented to demonstrate that CCD's can be applied advantageously to the problem of low power digital storage and particularly to the problem of interfacing widely varying data rates. 8K-bit CCD shift register memories were used to construct a feasibility model 128K-bit buffer memory system. Peak power dissipation during a data transfer is less than 7 W., while idle power is approximately 5.4 W. The system features automatic data input synchronization with the recirculating CCD memory block start address. Descriptions are provided of both the buffer memory system and a custom tester that was used to exercise the memory. The testing procedures and testing results are discussed. Suggestions are provided for further development with regards to the utilization of advanced versions of CCD memory devices to both simplified and expanded memory system applications

Single-Electron Traps: A Quantitative Comparison of Theory and Experiment

We have carried out a coordinated experimental and theoretical study of single-electron traps based on submicron aluminum islands and aluminum oxide tunnel junctions. The results of geometrical modeling using a modified version of MIT's FastCap were used as input data for the general-purpose single-electron circuit simulator MOSES. The analysis indicates reasonable quantitative agreement between theory and experiment for those trap characteristics which are not affected by random offset charges. The observed differences between theory and experiment (ranging from a few to fifty percent) can be readily explained by the uncertainty in the exact geometry of the experimental nanostructures.Comment: 17 pages, 21 figures, RevTex, eps

Chaotic dynamics in a storage-ring Free Electron Laser

The temporal dynamics of a storage-ring Free Electron Laser is here investigated with particular attention to the case in which an external modulation is applied to the laser-electron beam detuning. The system is shown to produce bifurcations, multi-furcations as well as chaotic regimes. The peculiarities of this phenomenon with respect to the analogous behavior displayed by conventional laser sources are pointed out. Theoretical results, obtained by means of a phenomenological model reproducing the evolution of the main statistical parameters of the system, are shown to be in a good agreement with experiments carried out on the Super-ACO Free Electron Laser.Comment: submitted to Europ Phys. Journ.

A procedural method for the efficient implementation of full-custom VLSI designs

An imbedded language system for the layout of very large scale integration (VLSI) circuits is examined. It is shown that through the judicious use of this system, a large variety of circuits can be designed with circuit density and performance comparable to traditional full-custom design methods, but with design costs more comparable to semi-custom design methods. The high performance of this methodology is attributable to the flexibility of procedural descriptions of VLSI layouts and to a number of automatic and semi-automatic tools within the system