Coarse-grained reconfigurable array architectures

Coarse-Grained Reconfigurable Array (CGRA) architectures accelerate the same inner loops that benefit from the high ILP support in VLIW architectures. By executing non-loop code on other cores, however, CGRAs can focus on such loops to execute them more efficiently. This chapter discusses the basic principles of CGRAs, and the wide range of design options available to a CGRA designer, covering a large number of existing CGRA designs. The impact of different options on flexibility, performance, and power-efficiency is discussed, as well as the need for compiler support. The ADRES CGRA design template is studied in more detail as a use case to illustrate the need for design space exploration, for compiler support and for the manual fine-tuning of source code

Modelling Heterogeneous DSP–FPGA Based System Partitioning with Extensions to the Spinach Simulation Environment

In this paper we present system-on-a-chip extensions to the Spinach simulation environment for rapidly prototyping heterogeneous DSP/FPGA based architectures, specifically in the embedded domain. This infrastructure has been successfully used to model systems varying from multiprocessor gigabit ethernet controllers to Texas Instruments C6x series DSP based systems with tightly coupled FPGA based coprocessors for computational offloading. As an illustrative example of this toolsets functionality, we investigate workload partitioning in heterogeneous DSP/FPGA based embedded environments. Specifically, we focus on computational offloading of matrix multiplication kernels across DSP/FPGA based embedded architectures

Investigating Single Precision Floating General Matrix Multiply in Heterogeneous Hardware

The fundamental operation of matrix multiplication is ubiquitous across a myriad of disciplines. Yet, the identification of new optimizations for matrix multiplication remains relevant for emerging hardware architectures and heterogeneous systems. Frameworks such as OpenCL enable computation orchestration on existing systems, and its availability using the Intel High Level Synthesis compiler allows users to architect new designs for reconfigurable hardware using C/C++. Using the HARPv2 as a vehicle for exploration, we investigate the utility of several of the most notable matrix multiplication optimizations to better understand the performance portability of OpenCL and the implications for such optimizations on this and future heterogeneous architectures. Our results give targeted insights into the applicability of best practices that were for existing architectures when used on emerging heterogeneous systems

Low-cost, multi-agent systems for planetary surface exploration

The use of off-the-shelf consumer electronics combined with top-down design methodologies have made small and inexpensive satellites, such as CubeSats, emerge as viable, low-cost and attractive space-based platforms that enable a range of new and exciting mission scenarios. In addition, to overcome some of the resource limitation issues encountered with these platforms, distributed architectures have emerged to enable complex tasks through the use of multiple low complexity units. The low-cost characteristics of such systems coupled with the distributed architecture allows for an increase in the size of the system beyond what would have been feasible with a monolithic system, hence widening the operational capabilities without significantly increasing the control complexity of the system. These ideas are not new for Earth orbiting devices, but excluding some distributed remote sensing architectures they are yet to be applied for the purpose of planetary exploration. Experience gained through large rovers demonstrates the value of in-situ exploration, which is however limited by the associated high-cost and risk. The loss of a rover can and has happened because of a number of possible failures: besides the hazards directly linked to the launch and journey to the target-body, hard landing and malfunctioning of parts are all threats to the success of the mission. To overcome these issues this paper introduces the concept of using off-the-shelf consumer electronics to deploy a low-cost multi-rover system for future planetary surface exploration. It is shown that such a system would significantly reduce the programmatic-risk of the mission (for example catastrophic failure of a single rover), while exploiting the inherent advantages of cooperative behaviour. These advantages are analysed with a particular emphasis put upon the guidance, navigation and control of such architectures using the method of artificial potential field. Laboratory tests on multi-agent robotic systems support the analysis. Principal features of the system are identified and the underlying advantages over a monolithic single-agent system highlighted