Design, implementation and testing of a real-time mobile WiMAX testbed featuring MIMO technology

Postprint (author’s final draft

Survey of FPGA applications in the period 2000 – 2015 (Technical Report)

Romoth J, Porrmann M, Rückert U. Survey of FPGA applications in the period 2000 – 2015 (Technical Report).; 2017.Since their introduction, FPGAs can be seen in more and more different fields of applications. The key advantage is the combination of software-like flexibility with the performance otherwise common to hardware. Nevertheless, every application field introduces special requirements to the used computational architecture. This paper provides an overview of the different topics FPGAs have been used for in the last 15 years of research and why they have been chosen over other processing units like e.g. CPUs

Role of Wireless technology in mobile augmented reality system (MARS)

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Synchronization algorithms and architectures for wireless OFDM systems

Orthogonal frequency division multiplexing (OFDM) is a multicarrier modulation technique that has become a viable method for wireless communication systems due to the high spectral efficiency, immunity to multipath distortion, and being flexible to integrate with other techniques. However, the high-peak-to-average power ratio and sensitivity to synchronization errors are the major drawbacks for OFDM systems. The algorithms and architectures for symbol timing and frequency synchronization have been addressed in this thesis because of their critical requirements in the development and implementation of wireless OFDM systems. For the frequency synchronization, two efficient carrier frequency offset (CFO) estimation methods based on the power and phase difference measurements between the subcarriers in consecutive OFDM symbols have been presented and the power difference measurement technique is mapped onto reconfigurable hardware architecture. The performance of the considered CFO estimators is investigated in the presence of timing uncertainty conditions. The power difference measurements approach is further investigated for timing synchronization in OFDM systems with constant modulus constellation. A new symbol timing estimator has been proposed by measuring the power difference either between adjacent subcarriers or the same subcarrier in consecutive OFDM symbols. The proposed timing metric has been realized in feedforward and feedback configurations, and different implementation strategies have been considered to enhance the performance and reduce the complexity. Recently, multiple-input multiple-output (MIMO) wireless communication systems have received considerable attention. Therefore, the proposed algorithms have also been extended for timing recovery and frequency synchronization in MIMO-OFDM systems. Unlike other techniques, the proposed timing and frequency synchronization architectures are totally blind in the sense that they do not require any information about the transmitted data, the channel state or the signal-to-noise-ratio (SNR). The proposed frequency synchronization architecture has low complexity because it can be implemented efficiently using the three points parameter estimation approach. The simulation results confirmed that the proposed algorithms provide accurate estimates for the synchronization parameters using a short observation window. In addition, the proposed synchronization techniques have demonstrated robust performance over frequency selective fading channels that significantly outperform other well-established methods which will in turn benefit the overall OFDM system performance. Furthermore, an architectural exploration for mapping the proposed frequency synchronization algorithm, in particular the CFO estimation based on the power difference measurements, on reconfigurable computing architecture has been investigated. The proposed reconfigurable parallel and multiplexed-stream architectures with different implementation alternatives have been simulated, verified and compared for field programmable gate array (FPGA) implementation using the Xilinx’s DSP design flow.EThOS - Electronic Theses Online ServiceMinistry of Higher Education and Scientific Research (MOHSR) of IraqGBUnited Kingdo

Radio Communications

In the last decades the restless evolution of information and communication technologies (ICT) brought to a deep transformation of our habits. The growth of the Internet and the advances in hardware and software implementations modified our way to communicate and to share information. In this book, an overview of the major issues faced today by researchers in the field of radio communications is given through 35 high quality chapters written by specialists working in universities and research centers all over the world. Various aspects will be deeply discussed: channel modeling, beamforming, multiple antennas, cooperative networks, opportunistic scheduling, advanced admission control, handover management, systems performance assessment, routing issues in mobility conditions, localization, web security. Advanced techniques for the radio resource management will be discussed both in single and multiple radio technologies; either in infrastructure, mesh or ad hoc networks

Multi-core architectures with coarse-grained dynamically reconfigurable processors for broadband wireless access technologies

Broadband Wireless Access technologies have significant market potential, especially the WiMAX protocol which can deliver data rates of tens of Mbps. Strong demand for high performance WiMAX solutions is forcing designers to seek help from multi-core processors that offer competitive advantages in terms of all performance metrics, such as speed, power and area. Through the provision of a degree of flexibility similar to that of a DSP and performance and power consumption advantages approaching that of an ASIC, coarse-grained dynamically reconfigurable processors are proving to be strong candidates for processing cores used in future high performance multi-core processor systems. This thesis investigates multi-core architectures with a newly emerging dynamically reconfigurable processor – RICA, targeting WiMAX physical layer applications. A novel master-slave multi-core architecture is proposed, using RICA processing cores. A SystemC based simulator, called MRPSIM, is devised to model this multi-core architecture. This simulator provides fast simulation speed and timing accuracy, offers flexible architectural options to configure the multi-core architecture, and enables the analysis and investigation of multi-core architectures. Meanwhile a profiling-driven mapping methodology is developed to partition the WiMAX application into multiple tasks as well as schedule and map these tasks onto the multi-core architecture, aiming to reduce the overall system execution time. Both the MRPSIM simulator and the mapping methodology are seamlessly integrated with the existing RICA tool flow. Based on the proposed master-slave multi-core architecture, a series of diverse homogeneous and heterogeneous multi-core solutions are designed for different fixed WiMAX physical layer profiles. Implemented in ANSI C and executed on the MRPSIM simulator, these multi-core solutions contain different numbers of cores, combine various memory architectures and task partitioning schemes, and deliver high throughputs at relatively low area costs. Meanwhile a design space exploration methodology is developed to search the design space for multi-core systems to find suitable solutions under certain system constraints. Finally, laying a foundation for future multithreading exploration on the proposed multi-core architecture, this thesis investigates the porting of a real-time operating system – Micro C/OS-II to a single RICA processor. A multitasking version of WiMAX is implemented on a single RICA processor with the operating system support

Phobos: The design and implementation of embedded software for a low cost radar warning receiver

This portfolio thesis describes work undertaken by the author under the Engineering Doctorate program of the Institute for System Level Integration. It was carried out in conjunction with the sponsor company Teledyne Defence Limited. A radar warning receiver is a device used to detect and identify the emissions of radars. They were originally developed during the Second World War and are found today on a variety of military platforms as part of the platform’s defensive systems. Teledyne Defence has designed and built components and electronic subsystems for the defence industry since the 1970s. This thesis documents part of the work carried out to create Phobos, Teledyne Defence’s first complete radar warning receiver. Phobos was designed to be the first low cost radar warning receiver. This was made possible by the reuse of existing Teledyne Defence products, commercial off the shelf hardware and advanced UK government algorithms. The challenges of this integration are described and discussed, with detail given of the software architecture and the development of the embedded application. Performance of the embedded system as a whole is described and qualified within the context of a low cost system

Channelization for Multi-Standard Software-Defined Radio Base Stations

As the number of radio standards increase and spectrum resources come under more pressure, it becomes ever less efficient to reserve bands of spectrum for exclusive use by a single radio standard. Therefore, this work focuses on channelization structures compatible with spectrum sharing among multiple wireless standards and dynamic spectrum allocation in particular. A channelizer extracts independent communication channels from a wideband signal, and is one of the most computationally expensive components in a communications receiver. This work specifically focuses on non-uniform channelizers suitable for multi-standard Software-Defined Radio (SDR) base stations in general and public mobile radio base stations in particular. A comprehensive evaluation of non-uniform channelizers (existing and developed during the course of this work) shows that parallel and recombined variants of the Generalised Discrete Fourier Transform Modulated Filter Bank (GDFT-FB) represent the best trade-off between computational load and flexibility for dynamic spectrum allocation. Nevertheless, for base station applications (with many channels) very high filter orders may be required, making the channelizers difficult to physically implement. To mitigate this problem, multi-stage filtering techniques are applied to the GDFT-FB. It is shown that these multi-stage designs can significantly reduce the filter orders and number of operations required by the GDFT-FB. An alternative approach, applying frequency response masking techniques to the GDFT-FB prototype filter design, leads to even bigger reductions in the number of coefficients, but computational load is only reduced for oversampled configurations and then not as much as for the multi-stage designs. Both techniques render the implementation of GDFT-FB based non-uniform channelizers more practical. Finally, channelization solutions for some real-world spectrum sharing use cases are developed before some final physical implementation issues are considered

An Introduction to Computer Networks

An open textbook for undergraduate and graduate courses on computer networks