Formal and Informal Methods for Multi-Core Design Space Exploration

We propose a tool-supported methodology for design-space exploration for embedded systems. It provides means to define high-level models of applications and multi-processor architectures and evaluate the performance of different deployment (mapping, scheduling) strategies while taking uncertainty into account. We argue that this extension of the scope of formal verification is important for the viability of the domain.Comment: In Proceedings QAPL 2014, arXiv:1406.156

Memory Bounds for the Distributed Execution of a Hierarchical Synchronous Data-Flow Graph

International audienceThis paper presents an application analysis technique to define the boundary of shared memory requirements of Multiprocessor System-on-Chip (MPSoC) in early stages of development. This technique is part of a rapid prototyping process and is based on the analysis of a hierarchical Synchronous Data-Flow (SDF) graph description of the system application. The analysis does not require any knowledge of the system architecture, the mapping or the scheduling of the system application tasks. The initial step of the method consists of applying a set of transformations to the SDF graph so as to reveal its memory characteristics. These transformations produce a weighted graph that represents the different memory objects of the application as well as the memory allocation constraints due to their relationships. The memory boundaries are then derived from this weighted graph using analogous graph theory problems, in particular the Maximum-Weight Clique (MWC) problem. Stateof-the-art algorithms to solve these problems are presented and a heuristic approach is proposed to provide a near-optimal solution of the MWC problem. A performance evaluation of the heuristic approach is presented, and is based on hierarchical SDF graphs of realistic applications. This evaluation shows the efficiency of proposed heuristic approach in finding near optimal solutions

Memory Bounds for the Distributed Execution of a Hierarchical Synchronous Data-Flow Graph

International audienceThis paper presents an application analysis technique to define the boundary of shared memory requirements of Multiprocessor System-on-Chip (MPSoC) in early stages of development. This technique is part of a rapid prototyping process and is based on the analysis of a hierarchical Synchronous Data-Flow (SDF) graph description of the system application. The analysis does not require any knowledge of the system architecture, the mapping or the scheduling of the system application tasks. The initial step of the method consists of applying a set of transformations to the SDF graph so as to reveal its memory characteristics. These transformations produce a weighted graph that represents the different memory objects of the application as well as the memory allocation constraints due to their relationships. The memory boundaries are then derived from this weighted graph using analogous graph theory problems, in particular the Maximum-Weight Clique (MWC) problem. Stateof-the-art algorithms to solve these problems are presented and a heuristic approach is proposed to provide a near-optimal solution of the MWC problem. A performance evaluation of the heuristic approach is presented, and is based on hierarchical SDF graphs of realistic applications. This evaluation shows the efficiency of proposed heuristic approach in finding near optimal solutions

Programação Robusta de Energia para Edifícios Inteligentes considerando a Incerteza em Veículos Eléctricos

Nos últimos anos, o consumo de energia tem aumentado juntamente com o crescimento económico e populacional, onde os edifícios representam um dos principais consumidores. Contudo, surgem preocupações a nível ambiental as quais inspiram governos a concentrarse na concepção de edifícios inteligentes com sistemas de gestão de energia que controlam as fontes de energia renováveis. No entanto, um fator importante a considerar ao lidar com os recursos energéticos é a natureza incerta do seu comportamento. De forma a dar resposta a este desafio, esta tese consiste em propor uma programação ótima dos recursos energéticos baseado na otimização robusta, tendo em conta as incertezas associadas aos veículos elétricos. A otimização robusta é uma abordagem inovadora e eficaz para resolver problemas de otimização que envolvem incerteza, uma vez que encontra a melhor solução entre os piores cenários possíveis. Inicialmente é formulada uma técnica de Redes Neuronais Artificiais, de modo a lidar com as incertezas. Posteriormente, um problema de Programação Linear Binária é estipulado para reduzir os custos energéticos do edíficio sem considerar incertezas. Numa fase final, o modelo determinístico é transformado num problema robusto, assegurando imunidade contra a incerteza associada aos veículos elétricos. De modo a simular o modelo de Otimização Robusta foram implementados três cenários diferentes de programação energética com um horizonte de tempo curto. Os resultados apresentaram uma redução de 14.86% no caso do estado da carga inicial, de 6.75% para a hora de chegada e de 14.18% para a hora de partida, revelando que o modelo implementado permite minimizar os custos totais de eletricidade de um edifício, bem como reduzir os problemas associados à incerteza dos veículos elétricos. Além disso, é demonstrado o ajustamento da técnica de otimização robusta de acordo com vários níveis de robustez.In recent years, electricity consumption has increased along with economic and population growth, with buildings representing one of the main consumers. However, environmental concerns are emerging and inspiring governments to focus on designing intelligent buildings with energy management systems that control renewable energy sources. However, an important factor to consider when dealing with energy resources is the uncertain nature of their behavior. To address this challenge, this thesis proposes optimal scheduling of energy resources based on robust optimization, taking into account the uncertainties associated with electric vehicles. Robust optimization is an innovative and effective approach for solving optimization problems involving uncertainty since it finds the best solution among the worst-case scenarios. Initially, an Artificial Neural Networks technique is formulated to deal with uncertainties. Afterward, a Binary Linear Programming problem is stipulated to reduce the energy costs of the building without considering uncertainties. In the final step, the deterministic model is transformed into a robust problem, ensuring immunity against the uncertainty related to electric vehicles. To simulate the Robust Optimization model, three different energy scheduling scenarios with a short time horizon were implemented. The results showed a reduction of 14.86% for the initial State Of Charge (SoC), 6.75% for the arrival time, and 14.18% for the departure time, revealing that the implemented model allows for minimizing the total electricity costs of a building, as well as reducing the problems associated with the uncertainty of electric vehicles. In addition, the adjustment of the robust optimization technique according to various levels of robustness is demonstrated

Design of multimedia processor based on metric computation

Media-processing applications, such as signal processing, 2D and 3D graphics rendering, and image compression, are the dominant workloads in many embedded systems today. The real-time constraints of those media applications have taxing demands on today's processor performances with low cost, low power and reduced design delay. To satisfy those challenges, a fast and efficient strategy consists in upgrading a low cost general purpose processor core. This approach is based on the personalization of a general RISC processor core according the target multimedia application requirements. Thus, if the extra cost is justified, the general purpose processor GPP core can be enforced with instruction level coprocessors, coarse grain dedicated hardware, ad hoc memories or new GPP cores. In this way the final design solution is tailored to the application requirements. The proposed approach is based on three main steps: the first one is the analysis of the targeted application using efficient metrics. The second step is the selection of the appropriate architecture template according to the first step results and recommendations. The third step is the architecture generation. This approach is experimented using various image and video algorithms showing its feasibility

Interference-Aware Scheduling for Connectivity in MIMO Ad Hoc Multicast Networks

We consider a multicast scenario involving an ad hoc network of co-channel MIMO nodes in which a source node attempts to share a streaming message with all nodes in the network via some pre-defined multi-hop routing tree. The message is assumed to be broken down into packets, and the transmission is conducted over multiple frames. Each frame is divided into time slots, and each link in the routing tree is assigned one time slot in which to transmit its current packet. We present an algorithm for determining the number of time slots and the scheduling of the links in these time slots in order to optimize the connectivity of the network, which we define to be the probability that all links can achieve the required throughput. In addition to time multiplexing, the MIMO nodes also employ beamforming to manage interference when links are simultaneously active, and the beamformers are designed with the maximum connectivity metric in mind. The effects of outdated channel state information (CSI) are taken into account in both the scheduling and the beamforming designs. We also derive bounds on the network connectivity and sum transmit power in order to illustrate the impact of interference on network performance. Our simulation results demonstrate that the choice of the number of time slots is critical in optimizing network performance, and illustrate the significant advantage provided by multiple antennas in improving network connectivity.Comment: 34 pages, 12 figures, accepted by IEEE Transactions on Vehicular Technology, Dec. 201