Simulation and Synthesis of Efficient Majority Logic Fault Detector Using EG-LDPC Codes to Reduce Access Time for Memory Applications

This paper presents an error-detection method for Euclidean Geometry low density parity check codes with majority logic decoding methodology in VHDL language and the output is verified with the help of Xilinx12.1. Majority logic decodable codes are suitable for memory applications due to their capability to correct a large number of errors. However, they require a large decoding time that impacts memory performance. The proposed fault-detection method significantly reduces memory access time when there is no error in the data read. The technique uses the majority logic decoder itself to detect failures, which makes the area overhead minimal and keeps the extra power consumption low. Starting from the original design of the ML decoder introduced, the proposed ML Detector/Decoder (MLDD) has been implemented using the Euclidean Geometry low density parity check codes. The proposed improved majority logic detector/decoder to perform data error correction in simple way using additional error correction technique and also reducing the delay time by detecting the errors in parallel manner. Hence the decoding process uses less number of cycles which reduces the delay

Comparison of channel coding schemes for molecular communications systems

Future applications for nano-machines, such as drug-delivery and health monitoring, will require robust communications and nanonetworking capabilities. This is likely to be enabled via the use of molecules, as opposed to electromagnetic waves, acting as the information carrier. To enhance the reliability of the transmitted data, Euclidean geometry low density parity check (EG-LDPC) and cyclic Reed-Muller (C-RM) codes are considered for use within a molecular communication system for the first time. These codes are compared against the Hamming code to show that an s = 4 LDPC (integer s ≥ 2) has a superior coding gain of 7.26 dBs. Furthermore, the critical distance and energy cost for a coded system are also taken into account as two other performance metrics. It is shown that when considering the case of nano-to nano-machines communication, a Hamming code with m = 4, (integer m ≥ 2) is better for a system operating between 10-6 and 10-3 bit error rate (BER) levels. Below these BERs,s = 2 LDPC codes are superior, exhibiting the lowest energy cost. For communication between nano-to macro-machines, and macro-to nano-machines, s = 3 LDPC and s = 2 LDPC are the best options respectively

An Elementary Proposal on Fault Tolerant Devices for Memory Scenario

The paper aims to propose as elementary work on a reliable memory system that can tolerate multiple transient errors in the memory words as well as multiple errors in the encoder and decoder (corrector) circuitry using one class of Error Correcting Codes i.e. type I 2-dimensional Euclidean Geometry Low-Density Parity-Check (EG-LDPC) codes and to quantify the importance of protecting encoder and corrector circuitry

LDPC-VBLAST for wireless communications

Recently, the demand for higher data rates of transmission has increased in many wireless communication applications. Using multi-transmit and multi-receive antennas has been shown to be a solution, since it can increase the channel capacity to accommodate higher transmission rates. Among the popular techniques developed to exploit the use of multiple antennas, VBLAST (Vertical Bell Laboratories Layered Space-Time) architecture can provide a very high spectral efficiency. However, in order to have better performance, an efficient error correction coding scheme with low complexity to implement is needed. In this study, we applied the Low density parity-check (LDPC) codes to the multi-transmit and multi receive antennas system, by combining Euclidean geometry LDPC codes with VBLAST system. Different code rates and different numbers of antennas are evaluated. By Monte-Carlo simulation, it is shown that the combination of both LDPC-VBLAST improves the bit error rate performance of the conventional one. Higher code rates improve further bit error rate performance while maintaining a high transmission data rate. LDPC-VBLAST can achieve nearly the lower bound performance of LDPC coding used with the multiple antennas optimum detector, maximum likelihood (ML) detector, when increasing the number of receive antennas. However, unlike ML detector, LDPC-VBLAST has lower complexity than ML detector when increasing the number of antennas. Thus, LDPC VBLAST can be suitable for using in many wireless applications

Applications of finite geometries to designs and codes

This dissertation concerns the intersection of three areas of discrete mathematics: finite geometries, design theory, and coding theory. The central theme is the power of finite geometry designs, which are constructed from the points and t-dimensional subspaces of a projective or affine geometry. We use these designs to construct and analyze combinatorial objects which inherit their best properties from these geometric structures. A central question in the study of finite geometry designs is Hamada’s conjecture, which proposes that finite geometry designs are the unique designs with minimum p-rank among all designs with the same parameters. In this dissertation, we will examine several questions related to Hamada’s conjecture, including the existence of counterexamples. We will also study the applicability of certain decoding methods to known counterexamples. We begin by constructing an infinite family of counterexamples to Hamada’s conjecture. These designs are the first infinite class of counterexamples for the affine case of Hamada’s conjecture. We further demonstrate how these designs, along with the projective polarity designs of Jungnickel and Tonchev, admit majority-logic decoding schemes. The codes obtained from these polarity designs attain error-correcting performance which is, in certain cases, equal to that of the finite geometry designs from which they are derived. This further demonstrates the highly geometric structure maintained by these designs. Finite geometries also help us construct several types of quantum error-correcting codes. We use relatives of finite geometry designs to construct infinite families of q-ary quantum stabilizer codes. We also construct entanglement-assisted quantum error-correcting codes (EAQECCs) which admit a particularly efficient and effective error-correcting scheme, while also providing the first general method for constructing these quantum codes with known parameters and desirable properties. Finite geometry designs are used to give exceptional examples of these codes

Fault Tolerant Nano-Memory with Fault Secure Encoder and Decoder

We introduce a nanowire-based, sublithographic memory architecture tolerant to transient faults. Both the storage elements and the supporting ECC encoder and corrector are implemented in dense, but potentially unreliable, nanowirebased technology. This compactness is made possible by a recently introduced Fault-Secure detector design [18]. Using Euclidean Geometry error-correcting codes (ECC), we identify particular codes which correct up to 8 errors in data words, achieving a FIT rate at or below one for the entire memory system for bit and nanowire transient failure rates as high as 10 −17 upsets/device/cycle with a total area below 1.7 × the area of the unprotected memory for memories as small as 0.1 Gbit. We explore scrubbing designs and show the overhead for serial error correction and periodic data scrubbing can be below 0.02 % for fault rates as high as 10 −20 upsets/device/cycle. We also present a design to unify the error-correction coding and circuitry used for permanent defect and transient fault tolerance

A STUDY OF LINEAR ERROR CORRECTING CODES

Since Shannon's ground-breaking work in 1948, there have been two main development streams of channel coding in approaching the limit of communication channels, namely classical coding theory which aims at designing codes with large minimum Hamming distance and probabilistic coding which places the emphasis on low complexity probabilistic decoding using long codes built from simple constituent codes. This work presents some further investigations in these two channel coding development streams. Low-density parity-check (LDPC) codes form a class of capacity-approaching codes with sparse parity-check matrix and low-complexity decoder Two novel methods of constructing algebraic binary LDPC codes are presented. These methods are based on the theory of cyclotomic cosets, idempotents and Mattson-Solomon polynomials, and are complementary to each other. The two methods generate in addition to some new cyclic iteratively decodable codes, the well-known Euclidean and projective geometry codes. Their extension to non binary fields is shown to be straightforward. These algebraic cyclic LDPC codes, for short block lengths, converge considerably well under iterative decoding. It is also shown that for some of these codes, maximum likelihood performance may be achieved by a modified belief propagation decoder which uses a different subset of 7^ codewords of the dual code for each iteration. Following a property of the revolving-door combination generator, multi-threaded minimum Hamming distance computation algorithms are developed. Using these algorithms, the previously unknown, minimum Hamming distance of the quadratic residue code for prime 199 has been evaluated. In addition, the highest minimum Hamming distance attainable by all binary cyclic codes of odd lengths from 129 to 189 has been determined, and as many as 901 new binary linear codes which have higher minimum Hamming distance than the previously considered best known linear code have been found. It is shown that by exploiting the structure of circulant matrices, the number of codewords required, to compute the minimum Hamming distance and the number of codewords of a given Hamming weight of binary double-circulant codes based on primes, may be reduced. A means of independently verifying the exhaustively computed number of codewords of a given Hamming weight of these double-circulant codes is developed and in coiyunction with this, it is proved that some published results are incorrect and the correct weight spectra are presented. Moreover, it is shown that it is possible to estimate the minimum Hamming distance of this family of prime-based double-circulant codes. It is shown that linear codes may be efficiently decoded using the incremental correlation Dorsch algorithm. By extending this algorithm, a list decoder is derived and a novel, CRC-less error detection mechanism that offers much better throughput and performance than the conventional ORG scheme is described. Using the same method it is shown that the performance of conventional CRC scheme may be considerably enhanced. Error detection is an integral part of an incremental redundancy communications system and it is shown that sequences of good error correction codes, suitable for use in incremental redundancy communications systems may be obtained using the Constructions X and XX. Examples are given and their performances presented in comparison to conventional CRC schemes

CONSTRUCTION OF FAULT RECOGNITION SYSTEM FOR MEMORY FUNCTIONS

The Error Correction Codes turn out to be most excellent way to alleviate soft errors in memory. The benefit of majority logic decoding is that it is extremely easy to put into practice and thus it is extremely realistic and has short difficulty. Several types of embedded memory are seen in approximately each and every system chip. Error detection within a block code can moreover be put into practice by computing syndrome as well as inspection of whether the entire its bits are zero.  We spotlight on using majority logic decoding circuitry itself like error detecting component consequently with no added hardware operations of read might be speed up. Novel version of majority logic decoder for getting better performance is accessible. The projected version makes use of equivalent decoding algorithm like one in plain majority logic decoder version. The introduced majority logic detector/decoder will be a well-organized design in support of fault detection as well as correction