Design and implementation of robust embedded processor for cryptographic applications

Practical implementations of cryptographic algorithms are vulnerable to side-channel analysis and fault attacks. Thus, some masking and fault detection algorithms must be incorporated into these implementations. These additions further increase the complexity of the cryptographic devices which already need to perform computationally-intensive operations. Therefore, the general-purpose processors are usually supported by coprocessors/hardware accelerators to protect as well as to accelerate cryptographic applications. Using a configurable processor is just another solution. This work designs and implements robust execution units as an extension to a configurable processor, which detect the data faults (adversarial or otherwise) while performing the arithmetic operations. Assuming a capable adversary who can injects faults to the cryptographic computation with high precision, a nonlinear error detection code with high error detection capability is used. The designed units are tightly integrated to the datapath of the configurable processor using its tool chain. For different configurations, we report the increase in the space and time complexities of the configurable processor. Also, we present performance evaluations of the software implementations using the robust execution units. Implementation results show that it is feasible to implement robust arithmetic units with relatively low overhead in an embedded processor

Методы функционального диагностирования ошибок шифрования в симметричных криптографических системах

Проведено аналіз існуючих рішень з виявлення несправностей та помилок у симетричних криптографічних системах. Розглянуто аналітичну модель поширення помилок. Запропоновано узагальнену методику діагностування помилок шифрування, яка базується на спільних операціях, які використовуються у більшості криптографічних алгоритмів.Known issues analysis of symmetric cryptographic systems fault detection is carried out. Analytic model for error coverage is considered. Generalized procedure for enciphering fault detection based on commonly used operations from most cryptographic algorithms is proposed

A new approach to ward off Error Propagation Effect of AES – Redundancy Based Technique Redefined

Advanced Encryption Standard (AES) [1, 2] is a great research challenge. It has been developed to replace the Data Encryption Standard (DES). AES suffers from a major limitation of Error propagation effect. To tackle this limitation, two methods are available. One is Redundancy Based Technique and the other one is Bite Based Parity Technique. The first one has a significant advantage of correcting any error on definite term over the second one but at the cost of higher level of overhead and hence lowering the processing speed. In this paper we have proposed a new approach based on the Redundancy Based Technique that would certainly speed up the process of reliable encryption and hence the secured communication. Keywords Advanced Encryption Standard, Error Propagation Effect, Redundancy Based Technique, Longitudinal Redundancy Check Cod

Relationship between problem-based learning experience and self-directed learning readiness

Tun Hussein Onn University of Malaysia (UTHM) has been implementing Problem-Based Learning (PBL) to some degree in various subjects. However, to this day no empirical data has been gathered on the effectiveness of PBL as a methodology to develop self-directed learning (SDL) skills. The purpose of this \ud study is to investigate self-directed learning readiness (SDLR) among UTHM students exposed to vaiying PBL exposure intensity. SDLR was measured using the modified version of Self-Directed Learning Readiness (SDLRS). Participants in this study were first-year undergraduate students at UTHM. The instrument was administrated to students in Electrical and Electronics Engineering, Civil and Environmental Engineering, and Technical Education (N=260). Data were analyzed using descriptive and inferential statistical techniques with analysis of variance (ANOVA) and the independent /'-test for equal variance for hypotheses testing. The results of this study indicate that overall SDLR level increase with PBL exposure up to exposure intensity twice, beyond which no increase in SDLR was observed with increase in PBL exposure. Within the same academic programme, results did not show a statistically significant difference of SDLR level between groups exposed to varying PBL exposure intensity. However, significant difference was found in some dimensions of the SDLR for the Technical Education students. Within the same education background, results did not show a statistically significant difference of SDLR level between groups exposed to varying PBL intensity. However, significant difference was found in some dimensions of the SDLR for students with both Matriculations and STPM background. A statistically significant difference of SDLR level was found between Electrical Engineering and Technical Education students for exposure once and in some SDLR dimensions. No statistically significant difference was found between students from different academic programme for exposure twice or thrice. The data supports the conclusion that SDLR level increases with increase in PBL exposure intensity up to a certain extent only, beyond which no increase of SDLR can be observed. The data also suggest that only certain dimensions of the SDLR improve with increased exposure to PBL

Lightweight protection of cryptographic hardware accelerators against differential fault analysis

© 2020 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes,creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works.Hardware acceleration circuits for cryptographic algorithms are largely deployed in a wide range of products. The HW implementations of such algorithms often suffer from a number of vulnerabilities that expose systems to several attacks, e.g., differential fault analysis (DFA). The challenge for designers is to protect cryptographic accelerators in a cost-effective and power-efficient way. In this paper, we propose a lightweight technique for protecting hardware accelerators implementing AES and SHA-2 (which are two widely used NIST standards) against DFA. The proposed technique exploits partial redundancy to first detect the occurrence of a fault and then to react to the attack by obfuscating the output values. An experimental campaign demonstrated that the overhead introduced is 8.32% for AES and 3.88% for SHA-2 in terms of area, 0.81% for AES and 12.31% for SHA-2 in terms of power with no working frequency reduction. Moreover, a comparative analysis showed that our proposal outperforms the most recent related countermeasures.Peer ReviewedPostprint (author's final draft

High-Speed Area-Efficient Hardware Architecture for the Efficient Detection of Faults in a Bit-Parallel Multiplier Utilizing the Polynomial Basis of GF(2m)

The utilization of finite field multipliers is pervasive in contemporary digital systems, with hardware implementation for bit parallel operation often necessitating millions of logic gates. However, various digital design issues, whether natural or stemming from soft errors, can result in gate malfunction, ultimately leading to erroneous multiplier outputs. Thus, to prevent susceptibility to error, it is imperative to employ an effective finite field multiplier implementation that boasts a robust fault detection capability. This study proposes a novel fault detection scheme for a recent bit-parallel polynomial basis multiplier over GF(2m), intended to achieve optimal fault detection performance for finite field multipliers while simultaneously maintaining a low-complexity implementation, a favored attribute in resource-constrained applications like smart cards. The primary concept behind the proposed approach is centered on the implementation of a BCH decoder that utilizes re-encoding technique and FIBM algorithm in its first and second sub-modules, respectively. This approach serves to address hardware complexity concerns while also making use of Berlekamp-Rumsey-Solomon (BRS) algorithm and Chien search method in the third sub-module of the decoder to effectively locate errors with minimal delay. The results of our synthesis indicate that our proposed error detection and correction architecture for a 45-bit multiplier with 5-bit errors achieves a 37% and 49% reduction in critical path delay compared to existing designs. Furthermore, the hardware complexity associated with a 45-bit multiplicand that contains 5 errors is confined to a mere 80%, which is significantly lower than the most exceptional BCH-based fault recognition methodologies, including TMR, Hamming's single error correction, and LDPC-based procedures within the realm of finite field multiplication.Comment: 9 pages, 4 figures. arXiv admin note: substantial text overlap with arXiv:2209.1338