Schottky power diodes designed for improved breakdown characteristics

Silicon carbide (SiC) is a semiconductor material sold as substrates (like silicon is) for making semiconductor devices. It has advantages (compared to other semiconductors like silicon) regarding making devices that operate at high temperature, high electric fields and high current density. Overall, the semiconductor industry continues to expand and SiC products are a growing part of this. In 2016, global semiconductor sales reached nearly US340 billion (the highest ever) according to The Semiconductor Industry Association (SIA). Market growth is driven by the ever-increasing amount of semiconductor technology in devices the world depends on for working (as reported by SIA). Power electronic components such as semiconductor SiC power diodes used in cars for example are among the numerous areas where improvements in performance are continually sought. ‘Increasing electrification in vehicles generally – and in hybrid and electric vehicles specifically is energizing the market for power semiconductors in vehicles’ (IHS Markit report). The HIS report shows that the total market for power semiconductors (including discrete SiC power diodes) will increase from US5.5 billion in 2016 to more than US$8.5 billion in 2022. An increasing trend towards electric cars in the coming years is expected to drive the demand for electronic components made from suitable semiconductor materials, including SiC. The advantage of SiC semiconductor chips is that they have high-reliability in harsh environments like the environment of the drive train of vehicles which includes the engine and connected components to deliver power to the wheels of vehicles. Moreover, the car industry is just one area where improvements in power semiconductor devices are sought. Anywhere where there is control, or high transmission voltage and current and voltage conversion, will benefit from improvement in diode performance. Two important aspects of Schottky diode performance are how much current it can deliver when in the forward bias mode and how much voltage it can withstand when in current blocking mode. Too much current (forward bias) or too much voltage (typically a reverse bias consideration) across the diode will cause it to break down. Considering the value of the power semiconductor device market, the industry push for performance, and the possibilities that improvements in SiC materials bring to semiconductor research, SiC Schottky diodes (also called Schottky Barrier Diodes, SBD) were investigated to determine the influence of several factors that affect device performance. Minimising the loss of energy and maximising the possible delivered electric current and also blocking voltage capability by improving SiC Schottky diode electrical performance is an important area of semiconductor research and of value to industry. Breakdown in the forward and reverse bias modes will be the focus of this research but the other aspects will also be reported on too. For example, high forward current is desired but if it comes at the expense of high forward voltage then there will be high power loss in the diode which should ideally act as a switch with no power loss. Similarly, a high reverse bias is desired but if leakage current (reverse bias current) is high then again there is power loss. This study uses finite element modelling and experimental investigation of different metals for forming improved Schottky contacts. Contact geometry and electrode edge isolation techniques are investigated to optimise designs. Schottky contact geometry is optimised in order to minimise the incidents of maximum current density within the diode structure, where breakdown occurs. Surface preparation and surface treatment prior to Schottky formation and in particular the surface treatments used to give a carbon-rich SiC surface, which in this research has been found to reduce the turn-on voltage of SiC Schottky diodes, is also investigated. Optimised geometry and electrode edge isolation improvements are demonstrated using silicon substrates and this improvement can be applied to any metal-to-semiconductor combination. A diode requires an Ohmic contact and this is also studied here with the approach of using selective etching to prepare the SiC surface. SiC diodes were fabricated and used for electrical testing to determine the electrical characteristics. Moreover, the effects of the quality of the SiC itself on the breakdown voltage was investigated (the major qualifier for crystal quality is the value of the density of the defect known as a micropipe and this value is called MPD (for micropipe density) and given in SiC wafer specifications from suppliers

7.86 kV GaN-on-GaN PN Power Diode with BaTiO3 for Electrical Field Management

Device based on GaN have great potential for high power switching applications due to its high breakdown field and high electron mobility. In this work, we present the device design of a vertical GaN-on-GaN PN power diode using high dielectric constant (high-k) dielectrics for electrical field management and high breakdown voltages, in together with guard-rings and a field plate. The fabricated diodes with a 57 um thick drift layer demonstrated a breakdown voltage of 7.86 kV on a bulk GaN substrate. The device has an on-resistance of 2.8 mohm.cm2 and a Baliga figure of merit of 22 GW/cm2.Comment: 4 pages, 6 figure

DC And RF Characterization Of n-GaN Schottky Diode For Microwave Application

Gallium nitride is a promising wide bandgap semiconductor material for high-power, high temperature and high frequency device applications. However, there are still a number of factors that are limiting the material to reach a satisfactory device performance. Among them the most important and critical factors are the reverse leakage current, series resistance, junction capacitance and thermal stability that limits Schottky diode performance on gallium nitride for Direct Current (DC) and Radio Frequency (RF) characteristics. To overcome these limitations we studied the influence of metal contact, contact area, thermal behavior and edge termination on DC and RF characteristics of n-GaN Schottky diode by simulation and fabrication approach

3.3 kV SiC JBS diodes employing a P2O5 surface passivation treatment to improve electrical characteristics

3.3 kV Schottky barrier diodes and Junction Barrier Schottky diodes have been fabricated, employing a phosphorous pentoxide (P2O5) surface treatment prior to metal deposition in an attempt to further condition the power device’s interface. For SBD structures, the treatment consistently reduces the leakage current in molybdenum, tungsten and niobium SBDs, for the tungsten treatment by more than four orders of magnitude. X-ray photoelectron spectroscopy (XPS) analysis on the treated SBD interface revealed formation of a metal phosphate between P2O5 and the metal. When compared to an untreated sample, the P2O5 treatment has increased the valence band to fermi level offset by 0.2 eV to 3.25 eV, indicating that the treatment results in a degenerately n-doped SiC surface. When applied to fully optimised 3.3 kV JBS power structures utilizing a hybrid JTE design, P2O5 treatments improved blocking capabilities across the entire dataset by as much as 1,000

A Low Temperature Co-fired Ceramic (LTCC) Interposer Based Three-Dimensional Stacked Wire Bondless Power Module

The objective of this dissertation research is to develop a low temperature co-fired ceramic (LTCC) interposer-based module-level 3-D wire bondless stacked power module. As part of the dissertation work, the 3-D wire bondless stack is designed, simulated, fabricated and characterized. The 3-D wire bondless stack is realized with two stand-alone power modules in a half-bridge configuration. Each stand-alone power module consists of two 1200 V 25 A silicon insulated-gate bipolar transistor (IGBT) devices in parallel and two 1200 V 20 A Schottky barrier diodes (SBD) in an antiparallel configuration. A novel interconnection scheme with conductive clamps and a spring loaded LTCC interposer is introduced to establish electrical connection between the stand-alone power modules to connect them in series to realize a half-bridge stack. Process development to fabricate the LTCC based 3-D stack is performed. In traditional power modules, wire bonds are used as a top side interconnections that introduce additional parasitic inductance in the current conduction path and prone to failure mechanism under high thermomechanical stresses. The loop inductance of the proposed 3-D half-bridge module exhibits 71% lower parasitic inductance compared to a wire bonded module. The 3-D stack exhibits better switching performance compared to the wire bonded counterpart. The measurement results for the 3-D stack shows 30% decrease in current overshoot at turn-on and 43% voltage overshoot at turn-off compared to the wire bonded module. Through measurements, it has been shown that the conducted noise reduces by 20 dB in the frequency range 20-30 MHz for the 3-D stack compared to the wire bonded counterpart. A simulation methodology using co-simulation techniques using ANSYS EM software tools is developed to predict EMI of a power module. Hardware verification of the proposed simulation methodology is performed to validate the co-simulation technique. The correlation coefficient between the measurement and simulation is found to be 0.73. It is shown that 53% of the variability in the simulation can be explained by the simulated result. Moreover, the simulated and measured amplitudes of the EMI spectrum closely match with each other with some variations due to round-off errors due to the FFT conversion

A walk on the frontier of energy electronics with power ultra-wide bandgap oxides and ultra-thin neuromorphic 2D materials

Altres ajuts: the ICN2 is funded also by the CERCA programme / Generalitat de CatalunyaUltra-wide bandgap (UWBG) semiconductors and ultra-thin two-dimensional materials (2D) are at the very frontier of the electronics for energy management or energy electronics. A new generation of UWBG semiconductors will open new territories for higher power rated power electronics and deeper ultraviolet optoelectronics. Gallium oxide - GaO(4.5-4.9 eV), has recently emerged as a suitable platform for extending the limits which are set by conventional (-3 eV) WBG e.g. SiC and GaN and transparent conductive oxides (TCO) e.g. In2O3, ZnO, SnO2. Besides, GaO, the first efficient oxide semiconductor for energy electronics, is opening the door to many more semiconductor oxides (indeed, the largest family of UWBGs) to be investigated. Among these new power electronic materials, ZnGa2O4 (-5 eV) enables bipolar energy electronics, based on a spinel chemistry, for the first time. In the lower power rating end, power consumption also is also a main issue for modern computers and supercomputers. With the predicted end of the Moores law, the memory wall and the heat wall, new electronics materials and new computing paradigms are required to balance the big data (information) and energy requirements, just as the human brain does. Atomically thin 2D-materials, and the rich associated material systems (e.g. graphene (metal), MoS2 (semiconductor) and h-BN (insulator)), have also attracted a lot of attention recently for beyond-silicon neuromorphic computing with record ultra-low power consumption. Thus, energy nanoelectronics based on UWBG and 2D materials are simultaneously extending the current frontiers of electronics and addressing the issue of electricity consumption, a central theme in the actions against climate chang

Study of Novel Power Semiconductor Devices for Performance and Reliability.

Power Semiconductor Devices are crucial components in present day power electronic systems. The performance and efficiency of the devices have a direct correlation with the power system efficiency. This dissertation will examine some of the components that are commonly used in a power system, with emphasis on their performance characteristics and reliability. In recent times, there has a proliferation of charge balance devices in high voltage discrete power devices. We examine the same charge balance concept in a fast recovery diode and a MOSFET. This is crucial in the extending system performance at compact dimensions. At smaller device and system sizes, the performance trade-off between the ON and OFF states becomes all the more critical. The focus on reducing the switching losses while maintaining system reliability increases. In a conventional planar technology, the technology places a limit on the switching performance owing to the larger die sizes. Using a charge balance structure helps achieve the improved trade-off, while working towards ultimately improving system reliability, size and cost. Chapter 1 introduces the basic power system based on an inductive switching circuit, and the various components that determine its efficiency. Chapter 2 presents a novel Trench Fast Recovery Diode (FRD) structure with injection control is proposed in this dissertation. The proposed structure achieves improved carrier profile without the need for excess lifetime control. This substantially improves the device performance, especially at extreme temperatures (-40oC to 175oC). The device maintains low leakage at high temperatures, and it\u27s Qrr and Irm do not degrade as is the usual case in heavily electron radiated devices. A 1600 diode using this structure has been developed, with a low forward turn-on voltage and good reverse recovery properties. The experimental results show that the structure maintains its performance at high temperatures. In chapter 3, we develop a termination scheme for the previously mentioned diode. A major limitation on the performance of high voltage power semiconductor is the edge termination of the device. It is critical to maintain the breakdown voltage of the device without compromising the reliability of the device by controlling the surface electric field. A good termination structure is critical to the reliability of the power semiconductor device. The proposed termination uses a novel trench MOS with buried guard ring structure to completely eliminate high surface electric field in the silicon region of the termination. The termination scheme was applied towards a 1350 V fast recovery diode, and showed excellent results. It achieved 98% of parallel plane breakdown voltage, with low leakage and no shifts after High Temperature Reverse Bias testing due to mobile ion contamination from packaging mold compound. In chapter 4, we also investigate the device physics behind a superjunction MOSFET structure for improved robustness. The biggest issue with a completely charge balanced MOSFET is decreased robustness in an Unclamped Inductive Switching (UIS) Circuit. The equally charged P and N pillars result in a flat electric field profile, with the peak carrier density closer to the P-N junction at the surface. This results in an almost negligible positive dynamic Rds-on effect in the MOSFET. By changing the charge profile of the P-column, either by increasing it completely or by implementing a graded profile with the heavier P on top, we can change the field profile and shift the carrier density deeper into silicon, increasing the positive dynamic Rds-on effect. Simulation and experimental results are presented to support the theory and understanding. Chapter 5 summarizes all the theories presented and the contributions made by them in the field. It also seeks to highlight future work to be done in these areas

MODELLING AND DESIGN OF DIAMOND POWER SEMICONDUCTOR DEVICES

With its remarkable electro-thermal properties such as the highest known thermal conductivity (~22 W/cm∙ K at room temperature) of any material, high hole mobility (>2000 cm2/V∙s), high critical electric field (>10 MV/cm), and large bandgap (5.47 eV), Diamond has overwhelming advantages over Silicon and wide bandgap semiconductors (WBG) for ultra-high voltage and high temperature applications (>3 kV and >450 K, respectively). However, despite its tremendous potential, fabricated devices based on this material have not yet delivered the expected high-performance. This is due to three main reasons: (i) the lack of consistent physical models and design approaches specific to diamond-based devices that could significantly accelerate their development; (ii) the absence of shallow acceptor and donor dopant species which has resulted in poor room temperature performance; (iii) the technological issues of the manufacturing process. With the principal aim of modelling the next generation of diamond devices, this Ph.D dissertation endeavours to numerically model the main electro-thermal properties of diamond devices for power electronic applications. Optimized unipolar mode diamond field effect transistors have been designed by means of finite element simulations and their performance has been assessed against the state-of-the-art diamond FETs. Particular attention is given to the static and dynamic properties of deep dopant levels and their effects in WBG semiconductor-based devices. Moreover, by means of a more global comparison technique and through accurate theoretical analysis, diamond FETs and diodes’ performance have been projected and compared with that of GaN and SiC devices. This work concludes with possible implementations of diamond devices in power converters and provides a roadmap of diamond devices for power electronics. These promising results give a new impetus to the rather small, but growing diamond community and enable future research in the field with the goal of bringing diamond to the commercial world.U.K. Engineering and Physical Sciences Research Council for the University of Cambridge Centre for Doctoral Training under Grant EP/M506485/

Vertical Gallium Nitride Power Devices: Fabrication and Characterisation

Efficient power conversion is essential to face the continuously increasing energy consumption of our society. GaN based vertical power field effect transistors provide excellent performance figures for power-conversion switches, due to their capability of handling high voltages and current densities with very low area consumption. This work focuses on a vertical trench gate metal oxide semiconductor field effect transistor (MOSFET) with conceptional advantages in a device fabrication preceded GaN epitaxy and enhancement mode characteristics. The functional layer stack comprises from the bottom an n+/n- drift/p body/n+ source GaN layer sequence. Special attention is paid to the Mg doping of the p-GaN body layer, which is a complex topic by itself. Hydrogen passivation of magnesium plays an essential role, since only the active (hydrogen-free) Mg concentration determines the threshold voltage of the MOSFET and the blocking capability of the body diode. Fabrication specific challenges of the concept are related to the complex integration, formation of ohmic contacts to the functional layers, the specific implementation and processing scheme of the gate trench module and the lateral edge termination. The maximum electric field, which was achieved in the pn- junction of the body diode of the MOSFET is estimated to be around 2.1 MV/cm. From double-sweep transfer measurements with relatively small hysteresis, steep subthreshold slope and a threshold voltage of 3 - 4 V a reasonably good Al2O3/GaN interface quality is indicated. In the conductive state a channel mobility of around 80 - 100 cm2/Vs is estimated. This obtained value is comparable to device with additional overgrowth of the channel. Further enhancement of the OFF-state and ON-state characteristics is expected for optimization of the device termination and the high-k/GaN interface of the vertical trench gate, respectively. From the obtained results and dependencies key figures of an area efficient and competitive device design with thick drift layer is extrapolated. Finally, an outlook is given and advancement possibilities as well as technological limits are discussed.:1 Motivation and boundary conditions 1.1 A comparison of competitive semiconductor materials 1.2 Vertical GaN device concepts 1.3 Target application for power switches 2 The vertical GaN MOSFET concept 2.1 Incomplete ionization of dopants 2.2 The pseudo-vertical approach 2.3 Considerations for the device OFF-state 2.3.1 The pn-junction in reverse operation 2.3.2 The gate trench MIS-structure in OFF-state 2.3.3 Dimensional constraints and field plates 2.4 Static ON-state and switching considerations 2.4.1 The pn-junction in forward operation 2.4.2 Resistance contributions 2.4.3 Device model and channel mobility 2.4.4 Threshold voltage and subthreshold slope 2.4.5 Interface and dielectric trap states in wide band semiconductors 2.4.6 The body bias effect 3 Fabrication and characterisation 3.1 Growth methods for GaN substrates and layers 3.2 Substrates and the desired starting material 3.2.1 Physical and micro-structural characterisation 3.2.2 Dislocations and impurities 3.3 Pseudo- and true-vertical MOSFET fabrication 3.3.1 Processing routes 3.3.2 Inductively-coupled plasma etching 3.3.3 Process flow modification 3.4 Electrical characterisation, structures and process control 3.4.1 Current voltage characterisation 3.4.2 C(V) measurements and charge carrier profiling 3.4.3 Cooperative characterisation structures 4 Properties of the functional layers 4.1 Morphology of the MOVPE grown layers 4.2 Hydrogen out-diffusion treatment 4.3 Morphology of the n+-source layer grown by MBE 4.4 N-type doping of the functional layers 4.5 P-type GaN by magnesium doping 4.6 Structural properties after the etching and gate module formation 4.7 Electrical layer characterization 4.7.1 Gate dielectric and interface evaluation 5 Pseudo- and true vertical device operation 5.1 Influences of the metal-line sheet resistance 5.2 Formation and characterisation of ohmic contacts 5.2.1 Ohmic contacts to n-type GaN 5.2.2 Ohmic contacts to p-GaN 5.3 The pn- body diode 5.4 MOSFET operation 5.4.1 ON-state and turn-ON operation 5.4.2 The body bias effect on the threshold voltage 5.4.3 Device OFF-state 6 Summary and conclusion 6.1 Device performance 6.2 Current limits of the vertical device technology 6.3 Possibilities for advancements Bibliography A Appendix A.1 Deduction: Forward diffusion current of the pn-diode A.2 Deduction: Operation regions in the EKV model Figures Tables Abbreviations Symbols Postamble and Acknowledgemen