Shortcomings in ground testing, environment simulations, and performance predictions for space applications

This paper addresses the issues involved in radiation testing of devices and subsystems to obtain the data that are required to predict the performance and survivability of satellite systems for extended missions in space. The problems associated with space environmental simulations, or the lack thereof, in experiments intended to produce information to describe the degradation and behavior of parts and systems are discussed. Several types of radiation effects in semiconductor components are presented, as for example: ionization dose effects, heavy ion and proton induced Single Event Upsets (SEUs), and Single Event Transient Upsets (SETUs). Examples and illustrations of data relating to these ground testing issues are provided. The primary objective of this presentation is to alert the reader to the shortcomings, pitfalls, variabilities, and uncertainties in acquiring information to logically design electronic subsystems for use in satellites or space stations with long mission lifetimes, and to point out the weaknesses and deficiencies in the methods and procedures by which that information is obtained

Air recovery assessment on high-pressure pneumatic systems

A computational simulation and experimental work of the fluid flow through the pneumatic circuit used in a stretch blow moulding machine is presented in this paper. The computer code is built around a zero-dimensional thermodynamic model for the air blowing and recycling containers together with a non-linear time-variant deterministic model for the pneumatic three stations single acting valve manifold, which, in turn, is linked to a quasi-one-dimensional unsteady flow model for the interconnecting pipes. The flow through the pipes accounts for viscous friction, heat transfer, cross-sectional area variation, and entropy variation. Two different solving methods are applied: the method of characteristics and the Harten-Lax-Van Leer (HLL) Riemann first-order scheme. The numerical model allows prediction of the air blowing process and, more significantly, permits determination of the recycling rate at each operating cycle. A simplified experimental set-up of the industrial process was designed, and the pressure and temperature were adequately monitored. Predictions of the blowing process for various configurations proved to be in good agreement with the measured results. In addition, a novel design of a valve manifold intended for the polyethylene terephthalate (PET) plastic bottle manufacturing industry is also presented.Peer ReviewedPostprint (author's final draft

An Experimental Study of Reduced-Voltage Operation in Modern FPGAs for Neural Network Acceleration

We empirically evaluate an undervolting technique, i.e., underscaling the circuit supply voltage below the nominal level, to improve the power-efficiency of Convolutional Neural Network (CNN) accelerators mapped to Field Programmable Gate Arrays (FPGAs). Undervolting below a safe voltage level can lead to timing faults due to excessive circuit latency increase. We evaluate the reliability-power trade-off for such accelerators. Specifically, we experimentally study the reduced-voltage operation of multiple components of real FPGAs, characterize the corresponding reliability behavior of CNN accelerators, propose techniques to minimize the drawbacks of reduced-voltage operation, and combine undervolting with architectural CNN optimization techniques, i.e., quantization and pruning. We investigate the effect of environmental temperature on the reliability-power trade-off of such accelerators. We perform experiments on three identical samples of modern Xilinx ZCU102 FPGA platforms with five state-of-the-art image classification CNN benchmarks. This approach allows us to study the effects of our undervolting technique for both software and hardware variability. We achieve more than 3X power-efficiency (GOPs/W) gain via undervolting. 2.6X of this gain is the result of eliminating the voltage guardband region, i.e., the safe voltage region below the nominal level that is set by FPGA vendor to ensure correct functionality in worst-case environmental and circuit conditions. 43% of the power-efficiency gain is due to further undervolting below the guardband, which comes at the cost of accuracy loss in the CNN accelerator. We evaluate an effective frequency underscaling technique that prevents this accuracy loss, and find that it reduces the power-efficiency gain from 43% to 25%.Comment: To appear at the DSN 2020 conferenc

Full-Scale Turbofan Demonstration of a Deployable Engine Air-Brake for Drag Management Applications

This paper presents the design and full-scale ground-test demonstration of an engine airbrake (EAB) nozzle that uses a deployable swirl vane mechanism to switch the operation of a turbofan's exhaust stream from thrust generation to drag generation during the approach and/or descent phase of flight. The EAB generates a swirling outflow from the turbofan exhaust nozzle, allowing an aircraft to generate equivalent drag in the form of thrust reduction at a fixed fan rotor speed. The drag generated by the swirling exhaust flow is sustained by the strong radial pressure gradient created by the EAB swirl vanes. Such drag-on-demand is an enabler to operational benefits such as slower, steeper, and/ or aeroacoustically cleaner flight on approach, addressing the aviation community's need for active and passive control of aeroacoustic noise sources and access to confined airports. Using NASA's technology readiness level (TRL) definitions, the EAB technology has been matured to a level of six, i.e., a fully functional prototype. The TRL-maturation effort involved design, fabrication, assembly, and ground-testing of the EAB's deployable mechanism on a full-scale, mixed-exhaust, medium-bypass-ratio business jet engine (Williams International FJ44-4A) operating at the upper end of typical approach throttle settings. The final prototype design satisfied a set of critical technology demonstration requirements that included (1) aerodynamic equivalent drag production equal to 15% of nominal thrust in a high-powered approach throttle setting (called dirty approach), (2) excess nozzle flow capacity and fuel burn reduction in the fully deployed configuration, (3) acceptable engine operability during dynamic deployment and stowing, (4) deployment time of 3-5 s, (5) stowing time under 0.5 s, and (6) packaging of the mechanism within a notional engine cowl. For a typical twin-jet aircraft application, a constantspeed, steep approach analysis suggests that the EAB drag could be used without additional external airframe drag to increase the conventional glideslope from 3 deg to 4.3 deg, with about 3 dB noise reduction at a fixed observer location.NASA Glenn Research Center (Contract No. NNX13CC78C

Design and Evaluation of a RISC-V based SoC for Satellite on-board Networking

Ponencia presentada en XXXVIII Conference on Design of Circuits and Integrated Systems - DCIS 2023, November 15-17, 2023, Málaga, Spain.SpaceWire is a communication protocol that has become widely used in spacecraft for connecting instruments to data processors, mass-memory, and control processors. Field-Programmable Gate Arrays (FPGAs) have been a popular choice for implementing SpaceWire nodes due to their flexibility to meet unique requirements of each program or product. This paper presents a comparative study of two implementations of SpaceWire nodes, based on two different FPGA technologies, AMD-Xilinx SRAM-based and Microchip (Microsemi) FLASH based. The study compares the resource requirements and estimated power consumption of both implementations, using the same HDL SpaceWire IP core, with the SRAM-based one incorporating a 32-bit Microblaze soft-CPU, and the FLASH based one using a 32-bit RISC-V CPU. The obtained results are compared, and the paper concludes that FLASH-based FPGAs are more suitable for applications that require high reliability, tamper resistance, and fast, reliable restarts. In contrast, SRAM-based FPGAs are preferred in applications that require high performance and reconfigurability. The study shows that both FPGA technologies are capable of implementing SpaceWire nodes effectively and efficiently, and designers can choose the technology that best suits the specific requirements of each project.This work has been supported, within the fund for research groups of the Basque university system IT1440-22, by the Department of Education and, within SOC4CRIS KK-2023/00015 and COMMUTE ZE-2021/00931 projects, by the Elkartek and Hazitek programs, both of the Basque Government; the latter also by the Ministerio de Ciencia e Innovación of Spain through the Centro para el Desarrollo Tecnológico Industrial (CDTI) within the project IDI-20220543, and through the Fondo Europeo de Desarrollo Regional 2014-2020 (FEDER funds)