Optimization analysis on car interior structure noise based on particle swarm optimization and RBF model

The car body’s noise transfer function reflects the acoustic characteristics between the car body structure and interior cavity, which has an important influence on the noise control in the driver’s cab. In this paper, the finite element models of the car body structure, car interior cavity and acoustic-structure coupling were built based on the car body acoustic-structure coupling of the car and the theory of noise transfer function, and car body’s noise transfer function from the excitation position to the driver’s ears was calculated. The mathematical model for optimization of the car interior structure noise was built with the root-mean-square value of the sound pressure level response at the interior reference point as the objective function, and the first-order torsional modal frequency and the overall car body mass as the constraint conditions. To reduce the optimization burdens, the design space of the variables was sampled by means of orthogonal experimental design during the optimization process, and the Radial Basis Function (RBF) models of the root-mean-square value of the sound pressure level response of the noise at the driver’s ears and first-order torsional modal frequency were built to replace the finite element models. Finally, the optimization scheme of the car body’s noise transfer function was acquired by means of Particle Swarm Optimization (PSO). The results show that the sound pressure peak within in the frequency band reduces by 2.35 dB after optimization. Meanwhile, the response curves of the noise at the driver’s ears before and after optimization were acquired by substituting the optimization scheme into the finite element model of acoustic-structure coupling. Compared with the predicted results of RBF model, the relative error of the optimized root-mean-square value of the sound pressure in the accurate model is only 0.18 %, which manifests the feasibility of the optimization scheme

Low-Noise Micro-Power Amplifiers for Biosignal Acquisition

There are many different types of biopotential signals, such as action potentials (APs), local field potentials (LFPs), electromyography (EMG), electrocardiogram (ECG), electroencephalogram (EEG), etc. Nerve action potentials play an important role for the analysis of human cognition, such as perception, memory, language, emotions, and motor control. EMGs provide vital information about the patients which allow clinicians to diagnose and treat many neuromuscular diseases, which could result in muscle paralysis, motor problems, etc. EEGs is critical in diagnosing epilepsy, sleep disorders, as well as brain tumors. Biopotential signals are very weak, which requires the biopotential amplifier to exhibit low input-referred noise. For example, EEGs have amplitudes from 1 μV [microvolt] to 100 μV [microvolt] with much of the energy in the sub-Hz [hertz] to 100 Hz [hertz] band. APs have amplitudes up to 500 μV [microvolt] with much of the energy in the 100 Hz [hertz] to 7 kHz [hertz] band. In wearable/implantable systems, the low-power operation of the biopotential amplifier is critical to avoid thermal damage to surrounding tissues, preserve long battery life, and enable wirelessly-delivered or harvested energy supply. For an ideal thermal-noise-limited amplifier, the amplifier power is inversely proportional to the input-referred noise of the amplifier. Therefore, there is a noise-power trade-off which must be well-balanced by the designers. In this work I propose novel amplifier topologies, which are able to significantly improve the noise-power efficiency by increasing the effective transconductance at a given current. In order to reject the DC offsets generated at the tissue-electrode interface, energy-efficient techniques are employed to create a low-frequency high-pass cutoff. The noise contribution of the high-pass cutoff circuitry is minimized by using power-efficient configurations, and optimizing the biasing and dimension of the devices. Sufficient common-mode rejection ratio (CMRR) and power supply rejection ratio (PSRR) are achieved to suppress common-mode interferences and power supply noises. Our design are fabricated in standard CMOS processes. The amplifiers’ performance are measured on the bench, and also demonstrated with biopotential recordings

Energy Efficient Low-Noise Neural Recording Amplifier With Enhanced Noise Efficiency Factor

This paper presents a neural recording amplifier array suitable for large-scale integration with multielectrode arrays in very low-power microelectronic cortical implants. The proposed amplifier is one of the most energy-efficient structures reported to date, which theoretically achieves an effective noise efficiency factor (NEF) smaller than the limit that can be achieved by any existing amplifier topology, which utilizes a differential pair input stage. The proposed architecture, which is referred to as a partial operational transconductance amplifier sharing architecture, results in a significant reduction of power dissipation as well as silicon area, in addition to the very low NEF. The effect of mismatch on crosstalk between channels and the tradeoff between noise and crosstalk are theoretically analyzed. Moreover, a mathematical model of the nonlinearity of the amplifier is derived, and its accuracy is confirmed by simulations and measurements. For an array of four neural amplifiers, measurement results show a midband gain of 39.4 dB and a -3-dB bandwidth ranging from 10 Hz to 7.2 kHz. The input-referred noise integrated from 10 Hz to 100 kHz is measured at 3.5 uVrms and the power consumption is 7.92 uW from a 1.8-V supply, which corresponds to NEF=3.35. The worst-case crosstalk and common-mode rejection ratio within the desired bandwidth are -43.5 dB and 70.1 dB, respectively, and the active silicon area of each amplifier is 256ux256u in 0.18 um complementary metal–oxide semiconductor technology

Diseño de un amplificador chopper de señales neuronales

En el presente trabajo de tesis se diseña un amplificador para ser utilizado como parte de un sistema de adquisición de señales neuronales. La topología elegida para el desarrollo fue la de cascodo plegado de una sola salida (single ended folded cascode), ubicando los moduladores chopper de manera que no haya limitación debido al ancho de banda. Debido a que este trabajo está enfocado a dispositivos implantables, se requiere de un bajo consumo de potencia, así como una pequeña área ocupada. A estos dos requerimientos se suma el de ruido, el cual es de gran importancia al ser esta la primera etapa del sistema. Se utilizó el software CADENCE para realizar distintas simulaciones que comprueban el correcto análisis realizado. Los resultados más importantes previo a la aplicación de la técnica chopper son: el ruido referido a la entrada de 2.92Vrms, con una potencia consumida de 36.78uW utilizando una fuente de alimentación de 3.3V, la ganancia de lazo abierto es de 102.1dB y la ganancia de lazo cerrado es de 45.88dB con un ancho de banda de 7.96kHz. El área ocupada por el circuito es de 0.0073mm2.Tesi

LOW POWER AND HIGH SIGNAL TO NOISE RATIO BIO-MEDICAL AFE DESIGN TECHNIQUES

The research work described in this thesis was focused on finding novel techniques to implement a low-power and noise Bio-Medical Analog Front End (BMEF) circuit technique to enable high-quality Electrocardiography (ECG) sensing. Usually, an ECG signal and several bio-medical signals are sensed from the human body through a pair of electrodes. The electrical characteristics of the very small amplitude (1u-10mV) signals are corrupted by random noise and have a significant dc offset. 50/60Hz power supply coupling noise is one of the biggest cross-talk signals compared to the thermally generated random noise. These signals are even AFE composed of an Instrumentation Amplifier (IA), which will have a better Common Mode rejection ratio (CMRR). The main function of the AFE is to convert the weak electrical Signal into large signals whose amplitude is large enough for an Analog Digital Converter (ADC) to detect without having any errors. A Variable Gain Amplifier (VGA) is sometimes required to adjust signal amplitude to maintain the dynamic range of the ADC. Also, the Bio-medical transceiver needs an accurate and temperature-independent reference voltage and current for the ADC, commonly known as Bandgap Reference Circuit (BGR). These circuits need to consume as low power as possible to enable these circuits to be powered from the battery. The work started with analysing the existing circuit techniques for the circuits mentioned above and finding the key important improvements required to reach the target specifications. Previously proposed IA is generated based on voltage mode signal processing. To improve the CMRR (119dB), we proposed a current mode-based IA with an embedded DC cancellation technique. State-of-the-art VGA circuits were built based on the degeneration principle of the differential pair, which will enable the variable gain purpose, but none of these techniques discussed linearity improvement, which is very important in modern CMOS technologies. This work enhances the total Harmonic distortion (THD) by 21dB in the worst case by exploiting the feedback techniques around the differential pair. Also, this work proposes a low power curvature compensated bandgap with 2ppm/0C temperature sensitivity while consuming 12.5uW power from a 1.2V dc power supply. All circuits were built in 45nm TSMC-CMOS technology and simulated with all the performance metrics with Cadence (spectre) simulator. The circuit layout was carried out to study post-layout parasitic effect sensitivity

Régulateurs "Waterfall" : une nouvelle topologie énergétique pour l'électronique

Ce travail décrit une nouvelle topologie d'alimentation qui apporte des bénéfices aux dispositifs portables et aux composants électroniques à faible consommation. À l'autre extrémité du spectre, il serait également applicable aux systèmes à tension de bus plus élevée, tels que les panneaux solaires et les véhicules électriques, qui doivent décomposer des tensions plus élevées en domaines utilisables. La nouvelle topologie, que nous avons nommée Waterfall regulator, est décrite dans le présent travail et nommée ainsi pour ses caractéristiques saillantes rappelant une chute en cascade. Ce dispositif ouvre de nouvelles perspectives pour les systèmes à très basse consommation, basse tension et courant faible. Le mode de fonctionnement consiste à diviser une source d'alimentation brute en plusieurs domaines de tension, qui peuvent ensuite être utilisés pour alimenter les éléments individuels d'un système ou plusieurs unités indépendantes. Nous décrivons ici le premier rapport sur la réussite de la version de recyclage de l'énergie de ce nouveau système. Le dispositif se caractérise par une série de régulateurs de tension à faible chute et de circuits de déversement de courant (pass MOSFET). Le régulateur partage le courant qui traverse sa charge respective et complète le courant du stade suivant par un déversoir de courant, selon les besoins. Le contrôle s'effectue via une architecture de contrôle en cascade et peut être étendu à des périphériques d'ordre supérieur.This work described a new power supply topology that benefits portable device and low power electronics. At the other end of the spectrum, it is also applicable to higher bus voltage systems like solar panels and electric vehicles that must split higher voltages into usable domains. The new topology, which we named waterfall regulator, is describe herein and named as such for its salient features reminiscent of a waterfall. It opens up a new realm of possibilities for supra low power, low voltage and low current systems. The mode of operation consists of splitting a raw supply source into smaller voltage domains which can then be used for powering individual element of a system or powering multiple independent units. We describe here the first report of successful energy recycling version of this novel system. The devices are composed of a series of low dropout voltage regulators and current spillways circuits (pass MOSFET). The regulators share current passing thought their respective load and supplement current through a current spillway as required. Control is achieved through a cascade architecture and can be scaled up to higher order devices

Systèmes intégrés pour l'hybridation vivant-artificiel : modélisation et conception d'une chaine de détection analogique adaptative

Version corrigée/Bioelectronics is a transdisciplinary field which develops interconnection devices between biological systems presenting electrical activity and the world of electronics. This communication with living tissues implies to observe the electrical activity of the cells and therefore requires an electronic acquisition chain.The use of Multi / Micro Electrode Array leads to systems that acquire a large numberof parallel channels, thus consumption and congestion of acquisition circuits have a significant impact on the viability of the system to be implanted.This thesis proposes two reflections about these acquisition circuits. One of these reflections relates to amplifier circuits, their input impedance and consumption; the other concerns an analogue action potentials detector, its modeling and optimization.These theoretical work leading to concrete results, an ASIC was designed, manufactured, tested and characterized in this thesis. This eight-channel ASIC therefore includes amplifiers and analogue action potentials detector and is the main contribution of this thesis.La bioélectronique est un domaine transdisciplinaire qui oeuvre, entre autres, àl’interconnexion entre des systèmes biologiques présentant une activité électrique et le monde de l’électronique. Cette communication avec le vivant implique l’observation de l’activité électrique des cellules considérées et nécessite donc une chaine d’acquisition électronique.L’utilisation de Multi/Micro Electrodes Array débouche sur des systèmes devant acquérir un grand nombre de canaux en parallèle, dès lors la consommation et l’encombrement des circuits d’acquisition ont un impact significatif sur la viabilité du système destiné à être implanté.Cette thèse propose deux réflexions à propos de ces circuits d’acquisition. Une ces des réflexions a trait aux circuits d’amplification, à leur impédance d’entrée et à leur consommation ; l’autre concerne un détecteur de potentiels d’action analogique, sa modélisation et son optimisation.Ces travaux théoriques ayant abouti à des résultats concrets, un ASIC a été conçu,fabriqué, testé et caractérisé au cours de cette thèse. Cet ASIC à huit canaux comporte donc des amplificateurs et des détecteurs de potentiels d’action analogiques et constitue le principal apport de ce travail de thèse

INTEGRATION OF CMOS TECHNOLOGY INTO LAB-ON-CHIP SYSTEMS APPLIED TO THE DEVELOPMENT OF A BIOELECTRONIC NOSE

This work addresses the development of a lab-on-a-chip (LOC) system for olfactory sensing. The method of sensing employed is cell-based, utilizing living cells to sense stimuli that are otherwise not easily sensed using conventional transduction techniques. Cells have evolved over millions of years to be exquisitely sensitive to their environment, with certain types of cells producing electrical signals in response to stimuli. The core device that is introduced here is comprised of living olfactory sensory neurons (OSNs) on top of a complementary metal-oxide-semiconductor (CMOS) integrated circuit (IC). This hybrid bioelectronic approach to sensing leverages the sensitivity of OSNs with the electronic signal processing capability of modern ICs. Intimately combining electronics with biology presents a number of unique challenges to integration that arise from the disparate requirements of the two separate domains. Fundamentally the obstacles arise from the facts that electronic devices are designed to work in dry environments while biology requires not only a wet environment, but also one that is precisely controlled and non-toxic. Design and modeling of such heterogeneously integrated systems is complicated by the lack of tools that can address the multiple domains and techniques required for integration, namely IC design, fluidics, packaging, and microfabrication, and cell culture. There also arises the issue of how to handle the vast amount of data that can be generated by such systems, and specifically how to efficiently identify signals of interest and communicate them off-chip. The primary contributions of this work are the development of a new packaging scheme for integration of CMOS ICs into fluidic LOC systems, a methodology for cross-coupled multi-domain iterative modeling of heterogeneously integrated systems, demonstration of a proof-of-concept bioelectronic olfactory sensor, and a novel event-based technique to minimize the bandwidth required to communicate the information contained in bio-potential signals produced by dense arrays of electrically active cells

Analog Front-End Circuits for Massive Parallel 3-D Neural Microsystems.

Understanding dynamics of the brain has tremendously improved due to the progress in neural recording techniques over the past five decades. The number of simultaneously recorded channels has actually doubled every 7 years, which implies that a recording system with a few thousand channels should be available in the next two decades. Nonetheless, a leap in the number of simultaneous channels has remained an unmet need due to many limitations, especially in the front-end recording integrated circuits (IC). This research has focused on increasing the number of simultaneously recorded channels and providing modular design approaches to improve the integration and expansion of 3-D recording microsystems. Three analog front-ends (AFE) have been developed using extremely low-power and small-area circuit techniques on both the circuit and system levels. The three prototypes have investigated some critical circuit challenges in power, area, interface, and modularity. The first AFE (16-channels) has optimized energy efficiency using techniques such as moderate inversion, minimized asynchronous interface for data acquisition, power-scalable sampling operation, and a wide configuration range of gain and bandwidth. Circuits in this part were designed in a 0.25μm CMOS process using a 0.9-V single supply and feature a power consumption of 4μW/channel and an energy-area efficiency of 7.51x10^15 in units of J^-1Vrms^-1mm^-2. The second AFE (128-channels) provides the next level of scaling using dc-coupled analog compression techniques to reject the electrode offset and reduce the implementation area further. Signal processing techniques were also explored to transfer some computational power outside the brain. Circuits in this part were designed in a 180nm CMOS process using a 0.5-V single supply and feature a power consumption of 2.5μW/channel, and energy-area efficiency of 30.2x10^15 J^-1Vrms^-1mm^-2. The last AFE (128-channels) shows another leap in neural recording using monolithic integration of recording circuits on the shanks of neural probes. Monolithic integration may be the most effective approach to allow simultaneous recording of more than 1,024 channels. The probe and circuits in this part were designed in a 150 nm SOI CMOS process using a 0.5-V single supply and feature a power consumption of only 1.4μW/channel and energy-area efficiency of 36.4x10^15 J^-1Vrms^-1mm^-2.PHDElectrical EngineeringUniversity of Michigan, Horace H. Rackham School of Graduate Studieshttp://deepblue.lib.umich.edu/bitstream/2027.42/98070/1/ashmouny_1.pd