Instruction level power consumption estimation for ArchC processors

Orientador: Rodolfo Jardim de AzevedoDissertação (mestrado) - Universidade Estadual de Campinas, Instituto de ComputaçãoResumo: A constante redução do tamanho e o conseqüente aumento do número de transistores em um mesmo chip faz com que a potência dissipada pelos circuitos digitais aumente exponencialmente. Esse fato, combinado com a crescente demanda por dispositivos portáteis, têm levado à uma crescente preocupação quanto ao consumo de energia. Quanto mais potência é dissipada mais calor é gerado e mais energia é gasta com o seu resfriamento. Como resultado, projetistas estão considerando cada vez mais o impacto de suas decisões nesse quesito. Atualmente, ADLs¹ têm sido utilizadas para projetar novos processadores. Essas linguagens descrevem o comportamento da arquitetura para cada ação ou instrução. ADLs, além de diminuirem o tempo de projeto, são úteis para descobrir problemas arquiteturais em um nível mais elevado. Nesse trabalho, foi desenvolvida uma ferramenta de estimativa de consumo de energia em nível de instrução utilizando-se como base a ADL ArchC e, como estudo de caso, um processador SPARCv8. Como resultado do uso da ferramenta desenvolvida, uma simulação de um programa com estimativa de consumo de energia pode ser realizada 100 vezes mais rápida, na média, em relação ao fluxo tradicionalAbstract: The constant reduction in size and consequential increase in number of transistors inside a chip causes an exponential growth in digital circuit power consumption. Combined with the growing demand for portable electronic devices, this has led to a rising concern about energy consumption. The more power is dissipated, the more heat is generated, and the more energy is spent in the cooling process. As a result, designers have been more and more considering the impact of their decisions on this matter. Currently, ADLs¹ are being used to design new processors. These languages describe the architectural behaviour for each action or instruction. Besides decreasing the time-to-market gap, ADLs are useful in discovering architectural problems at a higher level. This work presents an instruction leveI power estimation tool that uses ArchC ADL as a base, and a SPARCv8 processor as a case study. By using the developed tool, a simulation of a program with estimated power consumption can be accomplished 100 times faster, in average, than the traditional toolsMestradoSistemas de ComputaçãoMestre em Ciência da Computaçã

Energy/power consumption model for an embedded processor board

This dissertation, whose research has been conducted at the Group of Electronic and Microelectronic Design (GDEM) within the framework of the project Power Consumption Control in Multimedia Terminals (PCCMUTE), focuses on the development of an energy estimation model for the battery-powered embedded processor board. The main objectives and contributions of the work are summarized as follows: A model is proposed to obtain the accurate energy estimation results based on the linear correlation between the performance monitoring counters (PMCs) and energy consumption. the uniqueness of the appropriate PMCs for each different system, the modeling methodology is improved to obtain stable accuracies with slight variations among multiple scenarios and to be repeatable in other systems. It includes two steps: the former, the PMC-filter, to identify the most proper set among the available PMCs of a system and the latter, the k-fold cross validation method, to avoid the bias during the model training stage. The methodology is implemented on a commercial embedded board running the 2.6.34 Linux kernel and the PAPI, a cross-platform interface to configure and access PMCs. The results show that the methodology is able to keep a good stability in different scenarios and provide robust estimation results with the average relative error being less than 5%. Este trabajo fin de máster, cuya investigación se ha desarrollado en el Grupo de Diseño Electrónico y Microelectrónico (GDEM) en el marco del proyecto PccMuTe, se centra en el desarrollo de un modelo de estimación de energía para un sistema empotrado alimentado por batería. Los objetivos principales y las contribuciones de esta tesis se resumen como sigue: Se propone un modelo para obtener estimaciones precisas del consumo de energía de un sistema empotrado. El modelo se basa en la correlación lineal entre los valores de los contadores de prestaciones y el consumo de energía. Considerando la particularidad de los contadores de prestaciones en cada sistema, la metodología de modelado se ha mejorado para obtener precisiones estables, con ligeras variaciones entre escenarios múltiples y para replicar los resultados en diferentes sistemas. La metodología incluye dos etapas: la primera, filtrado-PMC, que consiste en identificar el conjunto más apropiado de contadores de prestaciones de entre los disponibles en un sistema y la segunda, el método de validación cruzada de K iteraciones, cuyo fin es evitar los sesgos durante la fase de entrenamiento. La metodología se implementa en un sistema empotrado que ejecuta el kernel 2.6.34 de Linux y PAPI, un interfaz multiplataforma para configurar y acceder a los contadores. Los resultados muestran que esta metodología consigue una buena estabilidad en diferentes escenarios y proporciona unos resultados robustos de estimación con un error medio relativo inferior al 5%

Microprocessor energy characterization and optimization through fast, accurate, and flexible simulation

Thesis (S.M.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2001.This electronic version was submitted by the student author. The certified thesis is available in the Institute Archives and Special Collections.Includes bibliographical references (p. 99-102).Energy dissipation is emerging as a key constraint for both high-performance and embedded microprocessor designs, requiring computer architects to consider energy in addition to performance when evaluating design decisions. A major limitation is the general difficulty in analyzing the energy impact of architectural and microarchitectural features without constructing detailed implementations and running slow simulations. This thesis first describes the design of a fast, accurate, and flexible circuit simulation tool which enables transition-sensitive studies of microprocessor energy consumption that would otherwise be impossible or impractical. With a simulation infrastructure in place, various optimizations are implemented that target the entire datapath and cache energy consumption. The individual energy optimizations are analyzed in detail, and the microprocessor design is characterized using various energy breakdowns and studies of the bit correlation between data values. This work shows that a few relatively simple energy-saving techniques can have a large impact in the implementation of an energy-efficient microprocessor. By fully characterizing the energy usage, this thesis establishes a coherent vision of microprocessor energy consumption, and serves as a basis and motivation for further energy optimizations.by Ronny Krashinsky.S.M

System-Level Power Estimation Methodology for MPSoC based Platforms

Avec l'essor des nouvelles technologies d'intégration sur silicium submicroniques, la consommation de puissance dans les systèmes sur puce multiprocesseur (MPSoC) est devenue un facteur primordial au niveau du flot de conception. La prise en considération de ce facteur clé dès les premières phases de conception, joue un rôle primordial puisqu'elle permet d'augmenter la fiabilité des composants et de réduire le temps d'arrivée sur le marché du produit final.Shifting the design entry point up to the system-level is the most important countermeasure adopted to manage the increasing complexity of Multiprocessor System on Chip (MPSoC). The reason is that decisions taken at this level, early in the design cycle, have the greatest impact on the final design in terms of power and energy efficiency. However, taking decisions at this level is very difficult, since the design space is extremely wide and it has so far been mostly a manual activity. Efficient system-level power estimation tools are therefore necessary to enable proper Design Space Exploration (DSE) based on power/energy and timing.VALENCIENNES-Bib. électronique (596069901) / SudocSudocFranceF

High-level Switching Activity Prediction Through Sampled Monitored Simulation

This paper presents a sample-based technique to predict the switching activity of digital circuits. It is an improvement to PowerSC, a SystemC library extension that enables a fast and easy-to-use way of gathering switching activity from SystemC descriptions. The experimental results reveal that it can dramatically reduce the monitoring time of the simulation, with a minimal loss of accuracy with respect to estimates provided by an industrial tool. Several tests realized in a case study with a real-world design obtained reductions in the monitoring time of up to 99% with average errors of no more than 0.05%. © 2005 IEEE.2005161166Klein, F., Azevedo, R., Araujo, G., Enabling High-level Switching Activity Estimation using SystemC (2005), Institute of Computing, UNICAMP, Tech. Rep. IC-05-17, Aug(2003) SystemC Language Reference Manual, , Revision 1.0 ed, SystemC InitiativeLiu, D., Svensson, C., Power consumption estimation in CMOS VLSI chips (1994) IEEE Journal of Solid-State Circuits, pp. 663-670. , JuneK. D. Müller-Glaser, K. Hirsch, and K. Neusinger, Estimating essential design characteristics to support project planning for ASIC design management, L. Goto, SatoshiTrevillyan, Ed. Santa Clara, CA: IEEE Computer Society Press, Nov. 1991, pp. 148-151Xakellis, M.G., Najm, F.N., Statistical estimation of the switching activity in digital circuits (1994) DAC '94: Proceedings of the 31st annual conference on Design automation, pp. 728-733. , ACM PressLandman, P.E., Rabaey, J.M., Activity-sensitive architectural power analysis (1996) IEEE Trans. on Computer-Aided Design of Integrated Circuits, pp. 571-587. , IEEE Computer Society Press, JuneRaghunathan, A., Dey, S., Jha, N.K., Register-transfer level estimation techniques for switching activity and power consumption (1996) Proc. of the 1996 IEEE/ACM international conference on CAD, pp. 158-165. , IEEE Computer SocietyGupta, S., Najm, F.N., Energy and peak-current per-cycle estimation at RTL (2003) IEEE Trans. Very Large Scale Integr. Syst, 11 (4), pp. 525-537Anton, M., Colonescu, I., Macii, E., Poncino, M., Fast characterization of RTL power macromodels (2001) IEEE Proc. of ICECS 2001, pp. 1591-1594Mehta, H., Owens, R.M., Irwin, M.J., Energy characterization based on clustering (1996) DAC '96: Proceedings of the 33rd annual conference on Design automation, pp. 702-707. , ACM PressYe, W., Vijaykrishnan, N., Kandemir, M., Irwin, M.J., The design and use of SimplePower: A cycle-accurate energy estimation tool (2000) DAC '00: Proceedings of the 37th conference on Design automation, pp. 340-345. , ACM PressPower Compiler User Guide, V-2003.12 ed., Synopsys Inc., December 2003(2004) ModelSim SE 5.8b User's Manual, , Mentor Graphics Corporation, JanuaryMP3 decoder IP www.brazilip.org.br, The Brazil-IP Project, see htt

An Efficient Framework For High-level Power Exploration

Although SystemC is considered the most promising language for system-on-chip functional modeling, it doesn't come with power modeling capabilities. This work presents PowerSC, a novel power estimation framework which instruments SystemC for power characterization, modeling and estimation. Since it is entirely based on SystemC, PowerSC allows consistent power modeling from the highest to the lowest abstraction level. Besides, the framework's API provides facilities to integrate alternative modeling techniques, either at the same or at different abstraction levels. As a result, the required power evaluation infrastructure is reduced to a minimum: the standard SystemC library, the PowerSC library itself and a C++ compiler. Experimental results show both the effectiveness and the efficiency of our framework. On the one hand, two well-known macromodeling techniques were easily integrated into the framework, leading to acceptable average errors at the RT level. On the other hand, library characterization was more than 13x faster as compared to a typical industrial flow. ©2007 IEEE.10461049(2002) SystemC 2.0 User's Guide, , Version 2.0 ed, OSCILiu, D., Svensson, C., Power consumption estimation in CMOS VLSI chips (1994) IEEE Journal of Solid-State Circuits, pp. 663-670. , JuneMüller-Glaser, K.D., Hirsch, K., Neusinger, K., Estimating essential design characteristics to support project planning for ASIC design management (1991) Proc of ICCAD, pp. 148-151. , NovLandman, P.E., Rabaey, J.M., Activity-sensitive architectural power analysis (1996) IEEE Trans. on Computer-Aided Design of Integrated Circuits, pp. 571-587. , JuneMehta, H., Owens, R.M., Irwin, M.J., Energy characterization based on clustering (1996) Proc. of DAC, pp. 702-707Raghunathan, A., Dey, S., Jha, N.K., Register-transfer level estimation techniques for switching activity and power consumption (1996) Proc. of the IEEE/ACM intern. conference on CAD, pp. 158-165Gupta, S., Najm, F.N., Energy and peak-current per-cycle estimation at RTL (2003) IEEE Trans. Very Large Scale Integr. Syst, 11 (4), pp. 525-537Anton, M., Colonescu, I., Macii, E., Poncino, M., Fast characterization of RTL power macromodels (2001) Proc. of ICECSYe, W., Vijaykrishnan, N., Kandemir, M., Irwin, M.J., The design and use of SimplePower: A cycle-accurate energy estimation tool (2000) Proc. of DAC, pp. 340-345Power Compiler User Guide, X-2005.09 ed., Synopsys Inc., 2005Nebel, W., Helms, D., High-level power estimation and analysis (2005) Low-Power Electronics Design, , CRC Press, ch. 38Stammermann, A., Kruse, L., Nebel, W., Pratsch, A., Schmidt, E., Schulte, M., Schulz, A., System level optimization and design space exploration for low power (2001) Proc. of the 14th international symposium on Systems synthesis, pp. 142-146Klein, F., Azevedo, R., Araujo, G., High-level switching activity prediction through sampled monitored simulation (2005) Proceedings of the International Symposyum on System-on-Chip 2005, , NovemberGupta, S., Najm, F.N., Power macromodeling for high level power estimation (1997) Design Automation Conference, pp. 365-370Macii, E., Poncino, M., Power macro-models for high-level power estimation (2005) Low-Power Electronics Design, , CRC Press, ch. 3

On The Limitations Of Power Macromodeling Techniques

Although RTL power macromodeling is a mature research topic, it is not yet broadly accepted in the industrial environment. One of the main reasons impairing its widespread use as a power estimation paradigm is that each macromodeling technique makes some assumptions that lead to some sort of intrinsic limitation, thereby affecting its accuracy. This paper discusses the limitations that can lead to unacceptably high estimation errors. First, a qualitative analysis uncovers the implicit assumptions and their resulting limitations. Then, a consistent set of experiments, performed on a same implementation framework, quantitatively compares three well-known macromodeling techniques. Experimental results show that each macromodel is more suitable for a specific region of the input space. Therefore, this work not only identifies the lack of robustness of each macromodel, but also provides proper grounds on how they should be safely combined towards a wider acceptance of the macromodel paradigm. © 2007 IEEE.395400Anton, M., Colonescu, I., Macii, E., Poncino, M., Fast characterization of RTL power macromodels (2001) IEEE Proc. of ICECS, pp. 1591-1594Barocci, M., Benini, L., Bogliolo, A., Ricco, B., Micheli, G.D., Lookup table power macro-models for behavioral library components (1999) IEEE Alessandro Volta Memorial Workshop on Low-Power Design, , MarchBogliolo, A., Benini, L., Robust rtl power macromodels (1998) IEEE TVLSI, 6 (4), pp. 578-581. , DecemberBruno, M., Macii, A., Poncino, M., A statistical power model for non-synthetic rtl operators (2003) PATMOS, pp. 208-218Corgnati, R., Macii, E., Poncino, M., Clustered table-based macromodels for rtl power estimation (1999) Proceedings of GLSVLSI, pp. 354-357Gupta, S., Najm, F.N., Power macromodeling for high level power estimation (1997) Proc. of DACGupta, S., Najm, F.N., Power modeling for high-level power estimation (2000) IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 8 (1), pp. 18-29. , FebruaryGupta, S., Najm, F.N., Energy and peak-current per-cycle estimation at RTL (2003) IEEE TVLSI, 11 (4), pp. 525-537Jochens, G., Kruse, L., Schmidt, E., Nebel, W., A new parameterizable power macro-model for datapath components (1999) Proc. of DATEJochens, G., Kruse, L., Schmidt, E., Stammermann, A., Nebel, W., Power macro-modelling for firm-macro (2000) PATMOS-00, pp. 24-35. , SeptemberKlein, F., Azevedo, R., Ara-jo, G., Enabling High-Level Switching Activity Estimation using SystemC (2005), Technical Report IC-05-17, IC-UNICAMP, AugLiu, X., Papaefthymiou, M.C., A markov chain sequence generator for power macromodeling (2004) IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 23 (7), pp. 1048-1062. , JulyMacii, E., Poncino, M., Power macro-models for high-level power estimation (2005) Low-Power Electronics Design, , chapter 39. CRC PressMehta, H., Owens, R.M., Irwin, M.J., Energy characterization based on clustering (1996) Proc. of DAC(2002) SystemC 2.0 User's Guide, , OSCI, 2.0 editionPowell, S.R., Chau, P.M., Estimating power dissipation of vlsi signal processing chips: The pfa technique (1990) VLSI Signal Processing, 4Raghunathan, A., Dey, S., Jha, N.K., Register-transfer level estimation techniques for switching activity and power consumption (1996) Proc. of ICCAD, pp. 158-165Wu, Q., Ding, C., Hsieh, C., Pedram, M., Statistical design of macro-models for rt-level power evaluation (1997) Proc. of ASPDA