Crosstalk Noise Analysis for Nano-Meter VLSI Circuits.

Scaling of device dimensions into the nanometer process technology has led to a considerable reduction in the gate delays. However, interconnect delays have not scaled in proportion to gate delays, and global-interconnect delays account for a major portion of the total circuit delay. Also, due to process-technology scaling, the spacing between adjacent interconnect wires keeps shrinking, which leads to an increase in the amount of coupling capacitance between interconnect wires. Hence, coupling noise has become an important issue which must be modeled while performing timing verification for VLSI chips. As delay noise strongly depends on the skew between aggressor-victim input transitions, it is not possible to a priori identify the victim-input transition that results in the worst-case delay noise. This thesis presents an analytical result that would obviate the need to search for the worst-case victim-input transition and simplify the aggressor-victim alignment problem significantly. We also propose a heuristic approach to compute the worst-case aggressor alignment that maximizes the victim receiver-output arrival time with current-source driver models. We develop algorithms to compute the set of top-k aggressors in the circuit, which could be fixed to reduce the delay noise of the circuit. Process variations cause variability in the aggressor-victim alignment which leads to variability in the delay noise. This variability is modeled by deriving closed-form expressions of the mean, the standard deviation and the correlations of the delay-noise distribution. We also propose an approach to estimate the confidence bounds on the path delay-noise distribution. Finally, we show that the interconnect corners obtained without incorporating the effects of coupling noise could lead to significant errors, and propose an approach to compute the interconnect corners considering the impact of coupling noise.Ph.D.Electrical EngineeringUniversity of Michigan, Horace H. Rackham School of Graduate Studieshttp://deepblue.lib.umich.edu/bitstream/2027.42/64663/1/gravkis_1.pd

On Co-Optimization Of Constrained Satisfiability Problems For Hardware Software Applications

Manufacturing technology has permitted an exponential growth in transistor count and density. However, making efficient use of the available transistors in the design has become exceedingly difficult. Standard design flow involves synthesis, verification, placement and routing followed by final tape out of the design. Due to the presence of various undesirable effects like capacitive crosstalk, supply noise, high temperatures, etc., verification/validation of the design has become a challenging problem. Therefore, having a good design convergence may not be possible within the target time, due to a need for a large number of design iterations. Capacitive crosstalk is one of the major causes of design convergence problems in deep sub-micron era. With scaling, the number of crosstalk violations has been increasing because of reduced inter-wire distances. Consequently only the most severe crosstalk faults are fixed pre-silicon while the rest are tested post-silicon. Testing for capacitive crosstalk involves generation of input patterns which can be applied post-silicon to the integrated circuit and comparison of the output response. These patterns are generated at the gate/ Register Transfer Level (RTL) of abstraction using Automatic Test Pattern Generation (ATPG) tools. In this dissertation, anInteger Linear Programming (ILP) based ATPG technique for maximizing crosstalk induced delay increase at the victim net, for multiple aggressor crosstalk faults, is presented. Moreover, various solutions for pattern generation considering both zero as well as unit delay models is also proposed. With voltage scaling, power supply switching noise has become one of the leading causes of signal integrity related failures in deep sub-micron designs. Hence, during power supply network design and analysis of power supply switching noise, computation of peak supply current is an essential step. Traditional peak current estimation approaches involve addition of peak current associated with all the CMOS gates which are switching in a combinational circuit. Consequently, this approach does not take the Boolean and temporal relationships of the circuit into account. This work presents an ILP based technique for generation of an input pattern pair which maximizes switching supply currents for a combinational circuit in the presence of integer gate delays. The input pattern pair generated using the above approach can be applied post-silicon for power droop testing. With high level of integration, Multi-Processor Systems on Chip (MPSoC) feature multiple processor cores and accelerators on the same die, so as to exploit the instruction level parallelism in the application. For hardware-software co-design, application programming model is based on a Task Graph, which represents task dependencies and execution/transfer times for various threads and processes within an application. Mapping an application to an MPSoC traditionally involves representing it in the form of a task graph and employing static scheduling in order to minimize the schedule length. Dynamic system behavior is not taken into consideration during static scheduling, while dynamic scheduling requires the knowledge of task graph at runtime. A run-time task graph extraction heuristic to facilitate dynamic scheduling is also presented here. A novel game theory based approach uses this extracted task graph to perform run-time scheduling in order to minimize total schedule length. With increase in transistor density, power density has gone up substantially. This has lead to generation of regions with very high temperature called Hotspots. Hotspots lead to reliability and performance issues and affect design convergence. In current generation Integrated Circuits (ICs) temperature is controlled by reducing power dissipation using Dynamic Thermal Management (DTM) techniques like frequency and/or voltage scaling. These techniques are reactive in nature and have detrimental effects on performance. Here, a look-ahead based task migration technique is proposed, in order to utilize the multitude of cores available in an MPSoC to eliminate thermal emergencies. Our technique is based on temperature prediction, leveraging upon a novel wavelet based thermal modeling approach. Hence, this work addresses several optimization problems that can be reduced to constrained max-satisfiability, involving integer as well as Boolean constraints in hardware and software domains. Moreover, it provides domain specific heuristic solutions for each of them

Statistical static timing analysis considering process variations and crosstalk

Increasing relative semiconductor process variations are making the prediction of realistic worst-case integrated circuit delay or sign-off yield more difficult. As process geometries shrink, intra-die variations have become dominant and it is imperative to model them to obtain accurate timing analysis results. In addition, intra-die process variations are spatially correlated due to pattern dependencies in the manufacturing process. Any statistical static timing analysis (SSTA) tool is incomplete without a model for signal crosstalk, as critical path delays can increase or decrease depending on the switching of capacitively coupled nets. The coupled signal timing in turn depends on the process variations. This work describes an SSTA tool that models signal crosstalk and spatial correlation in intra-die process variations, along with gradients and inter-die variations

Network-on-Chip

Addresses the Challenges Associated with System-on-Chip Integration Network-on-Chip: The Next Generation of System-on-Chip Integration examines the current issues restricting chip-on-chip communication efficiency, and explores Network-on-chip (NoC), a promising alternative that equips designers with the capability to produce a scalable, reusable, and high-performance communication backbone by allowing for the integration of a large number of cores on a single system-on-chip (SoC). This book provides a basic overview of topics associated with NoC-based design: communication infrastructure design, communication methodology, evaluation framework, and mapping of applications onto NoC. It details the design and evaluation of different proposed NoC structures, low-power techniques, signal integrity and reliability issues, application mapping, testing, and future trends. Utilizing examples of chips that have been implemented in industry and academia, this text presents the full architectural design of components verified through implementation in industrial CAD tools. It describes NoC research and developments, incorporates theoretical proofs strengthening the analysis procedures, and includes algorithms used in NoC design and synthesis. In addition, it considers other upcoming NoC issues, such as low-power NoC design, signal integrity issues, NoC testing, reconfiguration, synthesis, and 3-D NoC design. This text comprises 12 chapters and covers: The evolution of NoC from SoC—its research and developmental challenges NoC protocols, elaborating flow control, available network topologies, routing mechanisms, fault tolerance, quality-of-service support, and the design of network interfaces The router design strategies followed in NoCs The evaluation mechanism of NoC architectures The application mapping strategies followed in NoCs Low-power design techniques specifically followed in NoCs The signal integrity and reliability issues of NoC The details of NoC testing strategies reported so far The problem of synthesizing application-specific NoCs Reconfigurable NoC design issues Direction of future research and development in the field of NoC Network-on-Chip: The Next Generation of System-on-Chip Integration covers the basic topics, technology, and future trends relevant to NoC-based design, and can be used by engineers, students, and researchers and other industry professionals interested in computer architecture, embedded systems, and parallel/distributed systems

Methoden und Beschreibungssprachen zur Modellierung und Verifikation vonSchaltungen und Systemen: MBMV 2015 - Tagungsband, Chemnitz, 03. - 04. März 2015

Der Workshop Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV 2015) findet nun schon zum 18. mal statt. Ausrichter sind in diesem Jahr die Professur Schaltkreis- und Systementwurf der Technischen Universität Chemnitz und das Steinbeis-Forschungszentrum Systementwurf und Test. Der Workshop hat es sich zum Ziel gesetzt, neueste Trends, Ergebnisse und aktuelle Probleme auf dem Gebiet der Methoden zur Modellierung und Verifikation sowie der Beschreibungssprachen digitaler, analoger und Mixed-Signal-Schaltungen zu diskutieren. Er soll somit ein Forum zum Ideenaustausch sein. Weiterhin bietet der Workshop eine Plattform für den Austausch zwischen Forschung und Industrie sowie zur Pflege bestehender und zur Knüpfung neuer Kontakte. Jungen Wissenschaftlern erlaubt er, ihre Ideen und Ansätze einem breiten Publikum aus Wissenschaft und Wirtschaft zu präsentieren und im Rahmen der Veranstaltung auch fundiert zu diskutieren. Sein langjähriges Bestehen hat ihn zu einer festen Größe in vielen Veranstaltungskalendern gemacht. Traditionell sind auch die Treffen der ITGFachgruppen an den Workshop angegliedert. In diesem Jahr nutzen zwei im Rahmen der InnoProfile-Transfer-Initiative durch das Bundesministerium für Bildung und Forschung geförderte Projekte den Workshop, um in zwei eigenen Tracks ihre Forschungsergebnisse einem breiten Publikum zu präsentieren. Vertreter der Projekte Generische Plattform für Systemzuverlässigkeit und Verifikation (GPZV) und GINKO - Generische Infrastruktur zur nahtlosen energetischen Kopplung von Elektrofahrzeugen stellen Teile ihrer gegenwärtigen Arbeiten vor. Dies bereichert denWorkshop durch zusätzliche Themenschwerpunkte und bietet eine wertvolle Ergänzung zu den Beiträgen der Autoren. [... aus dem Vorwort

Variation-Tolerant and Voltage-Scalable Integrated Circuits Design

Ultra-low-voltage (ULV) operation where the supply voltage of the digital computing hardware is scaled down to the level near or below transistor threshold voltage (e.g. 300-500mV) is a key technique to achieve high computing energy efficiency. It has enabled many new exciting applications in the field of Internet of Things (IoT) devices and energy-constrained applications such as medical implants, environment sensors, and micro-robots. Ultra-low-voltage (ULV) operation is also commonly used with the emerging architectures that are often non Von-Neumann style to empower energy-efficient cognitive computing. One the biggest challenge in realizing ULV design is the large circuit delay variability. To guarantee functionality in the worst-case process, voltage, and temperature (PVT) condition, the traditional safety margin approach requires operating at a slower clock frequency or higher supply voltage which significantly limits the achievable energy efficiency of the hardware. To fully claim the energy efficiency of ULV, the large circuit delay variation needs to be adaptively handled. However, the existing adaptive techniques that are optimized for nominal supply voltage operation and traditional Von-Neumann architectures become inefficient for ULV designs and emerging architectures. This thesis presents adaptive techniques based on timing error detection and correction (EDAC) that are more suitable for the energy-constrained ULV designs and the emerging architectures. The proposed techniques are demonstrated in three test chips: (1) R-Processor: A 0.4V resilient processor with a voltage-scalable and low-overhead in-situ EDAC technique. It achieves 38% energy efficiency improvement or 2.3X throughput improvement as compared to the traditional safety margin approach. (2) A 450mV timing-margin-free waveform sorter for brain computer interface (BCI) microsystem. It achieves 49.3% higher energy efficiency and 35.6% higher throughput than the traditional safety margin approach. (3) Ultra-low-power and robust power-management system which consists of a microprocessor employing ULV EDAC, 63-ratio integrated switched-capacitor DC-DC converter, and a fully-digital error based regulation controller. In this thesis, we also explore circuits for emerging techniques. The first is temperature sensors for dynamic-thermal-management (DTM). The modern high-performance microprocessors suffer from ever-increasing power densities which has led to reliability concerns and increased cooling costs from excessive heat. In order to monitor and manage the thermal behavior, DTM techniques embed multiple temperature sensors and use its information. The size, accuracy, and voltage-scalability of the sensor are critical for the performance of DTM. Therefore, we propose a temperature sensor that directly senses transistor threshold voltage and the test chip demonstrates 9X smaller area, 3X higher accuracy, and 200mV lower voltage scalability (down to 400mV) than the previous state-of-art. Another area of exploration is interconnect design for ultra-dynamic-voltage-scaling (UDVS) systems. UDVS has been proposed for applications that require both high performance and high energy efficiency. UDVS can provide peak performance with nominal supply voltage when work load is high. When work load is moderate or low, UDVS systems can switch to ULV operation for higher energy efficiency. One of the critical challenges for developing UDVS systems is the inflexibility in various circuit fabrics that are often optimized for a single supply voltage. One critical example is conventional repeater based long interconnects which suffers from non-optimal performance and energy efficiency in UDVS systems. Therefore, in this thesis, we propose a reconfigurable interconnect design based on regenerators and demonstrate near optimal performance and energy efficiency across the supply voltage of 0.3V and 1V

Multi-level simulation of nano-electronic digital circuits on GPUs

Simulation of circuits and faults is an essential part in design and test validation tasks of contemporary nano-electronic digital integrated CMOS circuits. Shrinking technology processes with smaller feature sizes and strict performance and reliability requirements demand not only detailed validation of the functional properties of a design, but also accurate validation of non-functional aspects including the timing behavior. However, due to the rising complexity of the circuit behavior and the steady growth of the designs with respect to the transistor count, timing-accurate simulation of current designs requires a lot of computational effort which can only be handled by proper abstraction and a high degree of parallelization. This work presents a simulation model for scalable and accurate timing simulation of digital circuits on data-parallel graphics processing unit (GPU) accelerators. By providing compact modeling and data-structures as well as through exploiting multiple dimensions of parallelism, the simulation model enables not only fast and timing-accurate simulation at logic level, but also massively-parallel simulation with switch level accuracy. The model facilitates extensions for fast and efficient fault simulation of small delay faults at logic level, as well as first-order parametric and parasitic faults at switch level. With the parallelization on GPUs, detailed and scalable simulation is enabled that is applicable even to multi-million gate designs. This way, comprehensive analyses of realistic timing-related faults in presence of process- and parameter variations are enabled for the first time. Additional simulation efficiency is achieved by merging the presented methods in a unified simulation model, that allows to combine the unique advantages of the different levels of abstraction in a mixed-abstraction multi-level simulation flow to reach even higher speedups. Experimental results show that the implemented parallel approach achieves unprecedented simulation throughput as well as high speedup compared to conventional timing simulators. The underlying model scales for multi-million gate designs and gives detailed insights into the timing behavior of digital CMOS circuits, thereby enabling large-scale applications to aid even highly complex design and test validation tasks

Celebrating 120 Years of Butantan Institute Contributions for Toxinology

This is collection of original and review articles selected in recognition of the contribution of Instituto Butantan to the field of toxinology and its continued and relevant role in this field in the 120 years since its foundation. Congratulations to the Butantan Institute, its house scientists, and collaborators on its 120th anniversary

Hexavalent Chromium and Cancer Stem Cells: a view to a kill!

Tese de doutoramento em Biociências, no ramo de Biologia Molecular e Celular, apresentada ao Departamento de Ciências da Vida da Faculdade de Ciências e Tecnologia da Universidade de CoimbraContornando os avanços científicos feitos nas últimas décadas, o cancro prevalece como um grande problema de saúde pública que afeta milhões de pessoas por todo o mundo. O avanço mais recente feito no campo da oncobiologia foi a descoberta das células estaminais tumorais (CETs) e do seu envolvimento na doença metastática, a principal causa de morte em doentes oncológicos. Subsequentemente ficou demonstrado que as CETs regulam a tumorigenicidade e o grau de diferenciação tumoral, sendo ainda responsáveis pela resistência às terapias convencionais e pelas recidivas. Mais recentemente foram desenvolvidas terapias direcionadas especificamente a estas células que, no entanto, não surtiram o efeito esperado, uma vez as CETs conseguem regenerar- se por dediferenciação a partir de outras células do tumor. Os mecanismos subjacentes ao processo de dediferenciação são ainda desconhecidos, constituindo a sua caracterização parte dos objetivos deste trabalho. O cancro do pulmão é uma das neoplasias mais frequentes. A sua prevalência tem aumentado nos últimos anos, principalmente devido ao acréscimo dos hábitos tabágicos e à acumulação de poluentes atmosféricos. Neste trabalho utilizou-se o crómio hexavalente [Cr(VI)], um agente carcinogénico cujos níveis atmosféricos e relevância ocupacional têm aumentado significativamente nos últimos anos. Para os nossos estudos selecionámos uma linha celular não maligna de epitélio bronquial humano (BEAS-2B), a qual foi malignizada por cultura a baixa densidade na presença de Cr(VI), originando a linha celular RenG2. Em paralelo, uma linha controlo cultivada a baixa densidade na ausência de Cr(VI) (Cont1) foi também estabelecida. Visando aumentar o seu potencial maligno, as células RenG2 foram injetadas em murganhos imunocomprometidos e uma nova linha celular (DRenG2) foi estabelecida a partir do tumor formado. Este processo foi repetido com as células DRenG2, tendo-se obtido as células DDRenG2. Diversas técnicas de biologia celular e molecular foram então utilizadas para caracterizar os vários sistemas celulares, tendo os resultados obtidos sugerido o envolvimento de CETs na malignização das células BEAS-2B. Esta hipótese foi testada usando o ensaio de formação de esferas, no qual se observou a formação de colónias SC-DRenG2 e SC-DDRenG2, apenas nos dois sistemas derivados, DRenG2 e DDRenG2, respetivamente. Os resultados obtidos sugeriram que a formação de CETs na população de RenG2 injetada em murganhos imunocomprometidos decorreu de um processo de dediferenciação, provavelmente orquestrado pelas células do estroma do compartimento subcutâneo do animal. Para testar esta teoria, foram isoladas cirurgicamente células da região lombar de murganhos singénicos aos anteriores, e uma linha primária de fibroblastos (FR) foi estabelecida. A sua subsequente co-cultura com as células RenG2 durante dois meses levou à formação de uma população de CETs no seio das células RenG2 isoladas (iRenG2), cuja posterior caracterização mostrou serem mais semelhantes às DRenG2 e SC-DRenG2 do que às suas progenitoras RenG2. Por fim, o estudo dos meios condicionados das células em co-cultura identificou a Interleucina-6 (IL-6), o Factor estimulador de colónias derivado de granulócitos (G-CSF) e a Activina-A como potenciais mediadores parácrinos do processo de dediferenciação induzido pelas células do estroma do murganho.Bypassing all the research advances made in the last decades, cancer remains as a major public health problem affecting millions of people worldwide. The most recent advance in the tumor biology field was the discovery of cancer stem cells (CSCs) and of their implication in the metastatic disease, the main cause of cancer patients’ mortality. CSCs were shown to drive tumorigenesis and differentiation, contributing to tumors’ heterogeneity and to their chemo- and radiotherapy resistance and eventually relapse. Although targeted therapeutic approaches have been developed to abolish them, CSCs managed to reemerge through dedifferentiation of other tumor cells, condemning these therapies. The mechanisms behind dedifferentiation process are still unclear and were part of the main focus of this project. Lung cancer is one of the most common neoplasias worldwide. Its prevalence is increasing due to the widespread smoking habits and increasing accumulation of atmosphere pollutants. In this work hexavalent chromium [Cr(VI)] was selected as a model for lung carcinogenesis mainly due to is increasing occupational relevance. The nonmalignant human bronchial epithelial airway system 2B (BEAS-2B) was malignantly transformed into the RenG2 cell line using low density culture in the presence of Cr(VI). A parallel control cellular system (Cont1) was produced under the same conditions, though, in the absence of Cr(VI). Two additional derivative cell lines were attained following serial rounds of injection in immunocompromised mice, and named DRenG2 and DDRenG2, respectively. A panoply of techniques was then used to characterize the attained cellular systems leading to the hypothesis of CSCs involvement in Cr(VI)-driven BEAS-2B malignant transformation. The sphere-formation assay tested this hypothesis and allowed the isolation of CSC spheres (SC-DRenG2 and SC-DDRenG2 cells, respectively), but only from the derivative cell lines. These results suggested that a dedifferentiation process featured CSCs’ formation during RenG2 derivation in nude mice. The involvement of the mouse stroma in the dedifferentiation process was uncovered by surgical isolation of lumbar stromal cells (FR fibroblasts) from the subcutaneous compartment and their subsequent co-culture with RenG2 cells. Following two months, RenG2 cells were isolated from the upper compartment (iRenG2) and tested for their ability to form spheres. Gene and protein expression analysis were used to compare iRenG2 cells’ signature with those of RenG2, DRenG2 and SC-DRenG2, showing that iRenG2 cells were no longer similar to RenG2 but rather more close to both DRenG2 and SC-DRenG2. Finally, the study of the conditioned media from co-cultured cells identified interleukin-6 (IL-6), granulocyte colony-stimulating factor (G-CSF) and Activin-A as the potential paracrine orchestrators of this stromal-induced dedifferentiation process.FCT - SFRH/BD/33884/200