Electromigration time-to-failure analysis using a lumped element model

This thesis presents a theoretical and computer simulation of electromigration behaviour in the Integrated Circuit (IC) interconnection, with a particular emphasis on the analysis of the time-to-failure (TTF) produced through the Lumped Element model. The current and most accepted physical model for electromigration is the Stress Evolution Model which forms the basis for the development of the current Lumped Element Model. For early failures, and ignoring transport through the grain bulk, the problem reduces to that of solving the equations for stress evolution equation on the complex grain boundary networks which make the cluster sections of the near-bamboo interconnect. The present research attempts to show that the stress evolution in a grain boundary cluster network mimics the time development of the voltage on an equivalent, lumped CRC electrical network. [Continues.

Reliability of copper interconnects in integrated circuits

Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Materials Science and Engineering, 2007.Includes bibliographical references.As dimensions shrink and current densities increase, the reliability of metal interconnects becomes a serious concern. In copper interconnects, the dominant diffusion path is along the interface between the copper and the top passivation layer (usually Si3N4). One of the predominant failure mechanisms in Cu has been open-circuit failure due to electromigration-induced void nucleation and growth near the cathode ends of interconnect segments. However, results from accelerated electromigration tests show that the simple failure analyses based on simple void nucleation and growth can not explain the wide range of times-to-failure that are observed, suggesting that other types of failure mechanisms are present. In this thesis, by devising and performing unique experiments through the development of an electromigration simulation tool, unexpected complex failure mechanisms have been identified that have significant effects on the reliability of copper interconnects. A simulation tool was developed by implementing the one-dimensional non-linear differential equation model first described by Korhonen et al. By applying an implicit method (Backward Euler method), the calculation time was significantly reduced, and stability increased, compared to previous tools based on explicit methods (Forward Euler method).(cont.) The tool was crosschecked with experimental results by comparing void growth rates in simulations and experiments. Using this tool, one can simulate stress and atomic concentration states over the entire length of an interconnect segment or throughout a multi-segment interconnect tree, to identify analyze possible failure locations and mechanisms. Experiments were carried out on dotted-i structures, where two 25jim-lomg segments were connected by a via in the middle. Electrical currents were applied to the two segments independently, and lifetime effects of adjacent segments were determined. Using the simulation tool and calculations, it was shown that adjacent segments have a significant effect on a segment's stress state, even if the adjacent segment has no electrical current. This explains experimental observations. This also suggests that for reliability analyses to be accurate, the states of all adjacent segments must be considered, including the ones without electrical current. In a second set of experiments, the importance of pre-existing voids was investigated. Using in-situ scanning electron microscopy, voids away from the cathode were observed. These voids grew and drifted toward the cathode and the shape of the voids were found to be closely related to the texture and stress state of individual grains in the interconnect.(cont.) The drift velocity of voids was shown to be directly proportional to surface diffusivity. Electromigration tests on unpassivated samples were performed under vacuum to obtain the surface diffusivity of copper and its dependence on texture orientations. Simulation results show that pre-existing voids cause void growth away from the cathode. Subsequent failure mechanisms differ depending on the location of the pre-existing void and the critical void volume for de-pinning from grain boundaries. If pre-existing voids are present, void-growth-limited failure is expected in interconnects at low current densities, due to growth of pre-existing void, and the lifetimes are expected to scale inversely with j. However, at higher current densities (typical for accelerated testing), failure can occur through nucleation of new voids at the cathode (so that lifetimes scale inversely with j2), or through a mixture of nucleation of new voids and growth of pre-existing voids. These effects must be taken into account to accurately project the reliability of interconnects under service conditions, based on experiments carried out under accelerated conditions.by Zung-Sun Choi.Ph.D

Study of initial void formation and electron wind force for scaling effects on electromigration in Cu interconnects

textThe continuing scaling of integrated circuits beyond 22nm technology node poses increasing challenges to Electromigration (EM) reliability for Cu on-chip interconnects. First, the width of Cu lines in advanced technology nodes is less than the electron mean free path which is 39nm in Cu at room temperature. This is a new size regime where any new scaling effect on EM is of basic interest. And second, the reduced line width necessitates the development of new methods to analyze the EM characteristics. Such studies will require the development of well controlled processes to fabricate suitable test structures for EM study and model verification. This dissertation is to address these critical issues for EM in Cu interconnects. The dissertation first studies the initial void growth under EM, which is critical for measurement of the EM lifetime and statistics. A method based on analyzing the resistance traces obtained from EM tests of multi-link structures has been developed. The results indicated that there are three stages in the resistance traces where the rate of the initial void growth in Stage I is lower than that in Stage III after interconnect failure and they are linearly correlated. An analysis extending the Korhonen model has been formulated to account for the initial void formation. In this analysis, the stress evolution in the line during void growth under EM was analyzed in two regions and an analytic solution was deduced for the void growth rate. A Monte Carlo grain growth simulation based on the Potts model was performed to obtain grain structures for void growth analysis. The results from this analysis agreed reasonably well with the EM experiments. The next part of the dissertation is to study the size effect on the electron wind force for a thin film and for a line with a rectangular cross section. The electron wind force was modeled by considering the momentum transfer during collision between electrons and an atom. The scaling effect on the electron wind force was found to be represented by a size factor depending on the film/line dimensions. In general, the electron wind force is enhanced with increasing dimensional confinement. Finally, a process for fabrication of Si nanotrenches was developed for deposition of Cu nanolines with well-defined profiles. A self-aligned sub-lithographic mask technique was developed using polymer residues formed on Si surfaces during reactive ion etching of Si dioxide in a fluorocarbon plasma. This method was capable to fabricate ultra-narrow Si nanotrenches down to 20nm range with rectangular profiles and smooth sidewalls, which are ideal for studying EM damage mechanisms and model verification for future technology nodes.Physic

Effects of scaling and grain structure on electromigration reliability of Cu interconnects

textElectromigration (EM) remains a major reliability concern for on-chip Cu interconnects due to the continuing scaling and the introduction of new materials and processes. In Cu interconnects, the atomic diffusion along the Cu/SiCN cap interface dominates the mass transport and thus controls EM reliability. The EM lifetime degrades by half for each new generation due to the scaling of the critical void volume which induces the EM failure. To improve the EM performance, a metal cap such as CoWP was applied to the Cu surface to suppress the interfacial diffusion. By this approach, two orders of magnitude improvement in the EM lifetime was demonstrated. For Cu lines narrower than 90 nm, the Cu grain structure degraded from bamboo-like grains to polycrystalline grains due to the insufficient grain growth in the trench. Such a change in Cu grain structures can increase the mass transport through grain boundaries and thus degrade the EM performance. The objective of this study is to investigate the scaling effect on EM lifetime and Cu microstructure, and more importantly, the grain structure effect on EM behaviors of Cu interconnects with the CoWP cap compared to those with the SiCN cap only. This thesis is organized into three parts. In the first part, the effect of via scaling on EM reliability was studied by examining two types of specially designed test structures. The EM lifetime degraded with the via size scaling because the critical void size that causes the EM failure is the same with the via size. The line scaling effect on Cu grain structures were identified by examining Cu lines down to 60 nm in width using both plan-view and cross-sectional view transmission electron microscopy. In the second part, the effect of grain structure was investigated by examining the EM lifetime, statistics and failure modes for Cu interconnects with different caps. A more significant effect of the grain structure on EM characteristics was observed for the CoWP cap compared to the SiCN cap. For the CoWP cap, the grain structure not only affected the mass transport rate along the Cu line, but also impacted the flux divergence site distribution which determined the voiding location and the lifetime statistics. Finally, the effect of grain structure on EM characteristics of CoWP capped Cu interconnects was examined using a microstructure-based statistical model. In this model, the microstructure of Cu interconnects was simplified as cluster and bamboo grains connected in series. Based on the weakest-link approximation, it was shown that the EM lifetime and statistics could be adequately modeled by combining the measured cluster length distribution with the EM lifetime-cluster length correlation for each individual failure unit.Electrical and Computer Engineerin

New methodologies for interconnect reliability assessments of integrated circuits

Thesis (Ph.D.)--Massachusetts Institute of Technology, Dept. of Materials Science and Engineering, 2000.Includes bibliographical references (leaves 245-251).The stringent performance and reliability demands that will accompany the development of next-generation circuits and new metallization technologies will require new and more accurate means of assessing interconnect reliability. Reliability assessments based on conventional methodologies are flawed in a number of very important ways, including the disregard of the effects of complex interconnect geometries on reliability. New models, simulations and experimental methodologies are required for the development of tools for circuit-level and process-sensitive reliability assessments. Most modeling and experimental characterization of interconnect reliability has focused on simple straight lines terminating at pads or vias. However, laid-out integrated circuits usually have many interconnects with junctions and wide-to-narrow transitions. In carrying out circuit-level reliability assessments it is important to be able to assess the reliability of these more complex shapes, generally referred to as "trees". An interconnect tree consists of continuously connected high-conductivity metal within one layer of metallization. Trees terminate at diffusion barriers at vias and contacts, and, in the general case, can have more than one terminating branch when the tree includes junctions. We have extended the understanding of "immortality" demonstrated and analyzed for straight stud-to-stud lines, to trees of arbitrary complexity. We verified the concept of immortality in interconnect trees through experiments on simple tree structures. This leads to a hierarchical approach for identifying immortal trees for specific circuit layouts and models for operation. We suggest a computationally efficient and flexible strategy for assessment of the reliability of entire integrated circuits. The proposed hierarchical reliability analysis can provide reliability assessments during the design and layout process (Reliability Computer Aided Design, RCAD). Design rules are suggested based on calculations of the electromigration-induced development of inhomogeneous steadystate mechanical stress states. Failure of interconnects by void nucleation in single-layermetallization, as well as failure by void growth in the presence of refractory metal shunt layers are taken into account. The proposed methodology identifies a large fraction of interconnect trees in a typical design as immune to electromigration-induced failure. To complete a circuit-level-reliability analysis, it is also necessary to estimate the lifetimes of the mortal trees. We have developed simulation tools that allow modeling of stress evolution and failure in arbitrarily complex trees. We have demonstrated the validity of these models and simulations through comparisons with experiments on simple trees, such as "L"- and "T"-shaped trees with different current configurations. Because analyses made using simulations are computationally intensive, simulations should be used for analysis of the least reliable trees. The reliability of the majority of the mortal trees can be assessed using a conservative default model based on nodal reliability analyses for the assessment of electromigration-limited reliability of interconnect trees. The lifetimes of the nodes are calculated by estimating the times for void nucleation, void growth to failure, and formation of extrusions. The differences between straight stud-to-stud lines and interconnect trees are studied by investigating the effects of passive and active reservoirs on electromigration. Models and simulations were validated through comparisons with experiments on simple tree structures, such as lines broken into two limbs with different currents in each limb. Models, simulations and experimental results on the reliability of interconnect trees are shown to yield mutually consistent results. Taken together, the results from this research have provided the basis for the development of the first RCAD tool capable of accurate circuit-level, processing sensitive and layout-specific reliability analyses.by Stefan P. Hau-Riege.Ph.D

Microstructure evolution and interconnect realiability

Thesis (Ph.D.)--Massachusetts Institute of Technology, Dept. of Civil and Environmental Engineering, 2000.Includes bibliographical references (leaves 207-213).In the context of predicting the effects of geometry, microstructure, and processing conditions on electromigration (EM) induced interconnect failure, normal grain growth in thin films was studied, analytic models were built for the grain structure statistics in 2D and 3D interconnects, and simulation programs were developed for generation of process and complex-geometry-sensitive interconnect structures. The models were validated through simulations and experiments and were integrated into tools for circuit-design level interconnect reliability predictions. The universal scaling behavior of 2D normal grain growth was demonstrated and characterized using a simulation of 2D grain growth (GGSim). We showed that the constant rate of change of the average grain area is equal to the grain boundary mobility constant pt. We also found that the steady state grain size distribution obtained using our simulation technique, as well as those reported in experiments on simple model systems and those reported for very different simulation techniques, are all very well fit by a Weibull distribution function with the dimensionless parameter p = 5/2, and are better fit by this function than the log normal, Gamma or Rayleigh functions. The 2D simulation was used to simulate the development of film structures with drag induced lognormal grain size distributions from which interconnect strips were etched and then annealed, in order to analyze the statistics of as-patterned, as well as post-pattern annealed, interconnect grain structures. These statistics were characterized as a function of the ratios of the line-widths to the initial-grain-sizes. Among the important findings is that polygranular cluster and bamboo segment length distributions for as-patterned lines are best fit by Weibull distribution functions. Analytic formulae describing grain structure statistics were reported, for usage in EM simulations and reliability predictions. A differential model predicting the evolution of the polygranular cluster length distribution during post-patterning annealing was developed. It was shown that the rate of bamboo-segment nucleation per unit time and unit of untransformed length is proportional to [mu]/w 3 , and is negligible in the growth-dominated steady-state. The cluster shrinkage velocity was demonstrated to reach a constant steady-state value proportional to [mu]/w (assuming constant and uniform [mu]). This was shown to lead to a time-invariant, steady-state exponential cluster length distribution with an average cluster length proportional to the strip width, and a cluster length fraction decaying exponentially with U=[mu]/w2 . The distribution of grain lengths in the resulting final bamboo grain structure is well fit by a log normal distribution, with a median grain length scaling with the line width, and a line-width-independent normalized deviation in the grain length. This result was used to show, using an EM simulation, that grain-orientation-dependent variations in surface diffusivities constitute a likely cause for the variabilities in lifetimes observed experimentally. The 2D simulation GGSim was also substantially modified to simulate the patterning of interconnect features of general shapes from polygranular thin film structures, as well as to simulate further grain structure evolution due to post-patterning annealing in these complex shapes. A grain structure extraction tool, PolySeg, was developed to allow extraction of the atomic transport details in the case of complex interconnect trees for EM reliability predictions using EM simulations. To assess the 3D effects on grain structure evolution, and therefore on interconnect reliability, a soap froth experiment was used to study 3D normal grain growth in long rectangular prisms. The kinetics were found to scale with the normalized time [mu]/w 2 (with w being the largest of the two prism cross-sectional dimensions). It was found that the normalized duration of the conversion from 3D (non-columnar) to 2D (columnar) structures and the normalized duration of the initial phase during which the structure was polygranular became longer as w/h approached 1. The same results obtained in the 2D case for the scaling behaviors of the bamboo nucleation rate and the polygranular cluster shrinkage rate were demonstrated. Based on a 2D approach, a prism-geometry-sensitive analytic model was developed for the transformation to fully-bamboo structures. These results were compared with preliminary results obtained using a 3D grain growth simulation and qualitative agreement was demonstrated. We have successfully captured with simple analytic models as well as elaborate simulations the physics of microstructure evolution in complex patterned thin-film structures. In particular, we have developed an array of models and simulations that can be used to investigate the impact of geometry and process history on microstructure evolution, and ultimately on EM-induced failure statistics.by Walid R. Fayad.Ph.D

A CAD tool for the prediction of VLSI interconnect reliability.

Thesis (Ph.D.)-University of Natal, Durban, 1988.This thesis proposes a new approach to the design of reliable VLSI interconnects, based on predictive failure models embedded in a software tool for reliability analysis. A method for predicting the failure rate of complex integrated circuit interconnects subject to electromigration, is presented. This method is based on the principle of fracturing an interconnect pattern into a number of statistically independent conductor segments. Five commonly-occurring segment types are identified: straight runs, steps resulting from a discontinuity in the wafer surface, contact windows, vias and bonding pads. The relationship between median time-to-failure (Mtf) of each segment and physical dimensions, temperature and current density are determined. This model includes the effect of time-varying current density. The standard deviation of lifetime is also determined as a function of dimensions. A· minimum order statistical method is used to compute the failure rate of the interconnect system. This method, which is applicable to current densities below 106 AI cm2 , combines mask layout and simulation data from the design data base with process data to calculate failure rates. A suite of software tools called Reliant (RELIability Analyzer for iNTerconnects) which implements the algorithms described above, is presented. Reliant fractures a conductor pattern into segments and extracts electrical equivalent circuits for each segment. The equivalent circuits are used in conjunction with a modified version of the SPICE circuit simulator to determine the currents in all segments and to compute reliability. An interface to a data base query system provides the capability to access reliability data interactively. The performance of Reliant is evaluated, based on two CMOS standard cell layouts. Test structures for the calibration of the reliability models are provided. Reliant is suitable for the analysis of leaf cells containing a few hundred transistors. For MOS VLSI circuits, an alternative approach based on the use of an event-driven switch-level simulator is presented

Design tool and methodologies for interconnect reliability analysis in integrated circuits

Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2004.This electronic version was submitted by the student author. The certified thesis is available in the Institute Archives and Special Collections.Includes bibliographical references (p. 195-204).by Syed Mohiul Alam.Ph.D

STUDY OF TUNGSTEN NANOWIRES GROWN BY FIELD EMISSON INDUCED METHOD

Ph.DDOCTOR OF PHILOSOPH

Pulsed-Laser-Induced Melting and Solidification of Thin Metallic Films

This thesis focused on investigating excimer-laser induced melting and solidification of thin metallic films on SiO2. Two distinct topics were pursued: (1) microstructural manipulation and optimization of Cu films via SLS of as-deposited Cu films on SiO2, and (2) investigation of oriented heterogeneous nucleation via complete melting and subsequent nucleation-initiated solidification of Ni films on SiO2. The work on SLS of Cu films is motivated in large part by the need to improve the properties of Cu films which, among other applications, constitute an essential element in the continued evolution of microelectronic products. The experiments we have conducted show clearly that the film can be, without much difficulty, melted and solidified using pulsed-laser irradiation. Based on the findings from a series of systematic single-shot experiments, we show that SLS can be properly implemented to obtain large-grained Cu films with controlled microstructures and restricted textures. The lateral growth distance was found to increase as a function of increasing incident energy density. This observation is consistent with the findings that were made previously using other materials, and basically indicates that lateral solidification continues until the interface is halted by the interfaces growing from nucleated solids, which are triggered within the liquid matrix ahead of the growing interface. Close examination of the laterally grown grains, which quickly develop 100 rolling direction crystallographic orientation texture due to occlusion of differently oriented grains, reveal, furthermore, that low-angle grain boundaries as well as twins can be generated during the growth. These intra-grain defects are found to appear in a systematic manner (as they are located at specific regions and observed under specific incident energy densities). Significantly longer lateral growth distances observed in Cu films (compared to that of Si films) was attributed to the fact that substantially higher growth rates are expected with simple metallic films at a given interfacial undercooling. The implementation of SLS using Cu films was accomplished quite effectively, as can be expected from the above lateral-growth-related results involving single-shot experiments. We were able to achieve a variety of large-grained, grain-boundary location and grain-orientation controlled Cu films via various SLS techniques. When performed optimally in accordance with the findings made in chapter 2, the resulting microstructure exhibits large grains, which are primarily devoid of intra-grain defects. For example, 2-shot SLS processed Cu films led to strong 100 rolling direction orientation, while avoiding the formation of low-angle grain boundaries and twin-boundaries. The highlight of SLS on Cu films correspond to a version of SLS (referred to as "2-Shot plus 2-Shot" SLS) in which the second 2-shot SLS is performed in the direction perpendicular to the first one. Through this approach, we were able to achieve grain-boundary-location controlled microstructure with a strong 100 orientation texture in all three dimensions (forming, effectively, an ultra-large quasi-single crystal material). Nucleation of solids in laser-quenched Ni films was investigated using EBSD analysis. The surface orientation analysis of nucleated grains obtained within the complete melting regime reveal a clear sign of texture. From these and additional findings from previous work involving Al films, we were able to conclude that systematic heterogeneous nucleation has taken place, and, furthermore, that oriented nucleation of the solids must have taken place. Although always suspected to be the case, it is typically extremely challenging to prove with certainty, in conventional nucleation experiments, that the mechanism of nucleation corresponds to that of a heterogeneous one. Furthermore, although it has been suspected theoretically for over 50 years, experimental results that clearly show that oriented nucleation actually transpires have not been obtained until our work involving Al films; the present findings involving Ni films further strengthen this conclusion as the Ni system removes some of the experimental uncertainties that are associated with Al films, and, furthermore, suggests that the process of oriented nucleation is a general and rather pervasive phenomenon. Additionally, it was observed that the selected orientation changed as a function of incident energy density; in the low energy density regime (above the completed melting threshold) {110}-surface texture was observed, while {111}-surface texture became more dominent at higher densities. Motivated by our experimental work involving Al and Ni that clearly indicates that oriented heterogeneous nucleation is a major path through which heterogeneous nucleation of solids occurs, we have also carried out a 2-dimensional Winterbottom-type thermodynamic analysis that can be used to obtain a better understanding of the phenomenon. In contrast to the previous work on the subject, we consider in our modelling the anisotropic nature of both the solid-liquid and solid-substrate interfacial energy; we advocate that this is the only physically consistent combination. The results show that oriented nucleation can be systematically accounted for as stemming from the expected anisotropic nature of the involved interfacial energies. Furthermore, the analysis also suggests possible reasons for observing a transition in surface texture from one orientation to another