290 research outputs found
Modelling and analysis of crosstalk in scaled CMOS interconnects
The development of a general coupled RLC interconnect model for simulating scaled bus structures m VLSI is presented. Several different methods for extracting submicron resistance, inductance and capacitance parameters are documented. Realistic scaling dimensions for deep submicron design rules are derived and used within the model. Deep submicron HSPICE device models are derived through the use of constant-voltage scaling theory on existing 0.75µm and 1.0µm models to create accurate interconnect bus drivers. This complete model is then used to analyse crosstalk noise and delay effects on multiple scaling levels to determine the dependence of crosstalk on scaling level. Using this data, layout techniques and processing methods are suggested to reduce crosstalk in system
HIGH PERFORMANCE CLOCK DISTRIBUTION FOR HIGH-SPEED VLSI SYSTEMS
Tohoku University堀口 進課
Characterisation of crosstalk defects in submicron CMOS VLSI interconnects
The main problem addressed in this research work is a crosstalk defect, which is defined as an unexpected signal change due to the coupling between signals or power lines. Here its characteristic under 3 proposed models is investigated to find whether such a noise could lead to real logic faults in IC systems. As a result, mathematical analysis for various bus systems was established, with 3 main factors found to determine the amount of crosstalk: i) how the input buffers are sized; ii) the physical arrangements of the tracks; and iii) the number of switching tracks involved. Minimum sizes of the width and separation lead to the highest crosstalk while increasing in the length does not contribute much variation. Higher level of crosstalk is also found in higher metal layers due mainly to the reduced capacitance to the substrate. The crosstalk is at its maximum when the track concerned is the middle track of a bus connected to a weak buffer while the other signal lines are switching. From this information, the worse-case analysis for various bus configurations is proposed for 0.7, 0.5 and 0.35 µ CMOS technologies. For most of conventional logic circuits, a crosstalk as large as about a half of the supply voltage is required if a fault is to occur. For the buffer circuits the level of crosstalk required depends very much on the transition voltage, which is in turn controlled by the sizing of its n and p MOS transistors forming the buffer. It is concluded that in general case if crosstalk can be kept to be no larger that 30% of the supply voltage the circuit can be said to be very reliable and virtually free from crosstalk fault. Finally test structures are suggested so that real measurements can be made to verify the simulation result
3D modeling and integration of current and future interconnect technologies
Title from PDF of title page viewed June 21, 2021Dissertation advisor: Masud H. ChowdhuryVitaIncludes bibliographical references (pages 133-138)Thesis (Ph.D.)--School of Computing and Engineering and Department of Physics and Astronomy. University of Missouri--Kansas City, 2021To ensure maximum circuit reliability it is very important to estimate the circuit
performance and signal integrity in the circuit design phase. A full phase simulation for
performance estimation of a large-scale circuit not only require a massive computational
resource but also need a lot of time to produce acceptable results. The estimation of
performance/signal integrity of sub-nanometer circuits mostly depends on the interconnect
capacitance. So, an accurate model for interconnect capacitance can be used in the circuit
CAD (computer-aided design) tools for circuit performance estimation before circuit
fabrication which reduces the computational resource requirement as well as the time
constraints. We propose a new capacitance models for interconnect lines in multilevel
interconnect structures by geometrically modeling the electrical flux lines of the interconnect
lines. Closed-form equations have been derived analytically for ground and coupling
capacitance. First, the capacitance model for a single line is developed, and then the new
model is used to derive expressions for the capacitance of a line surrounded by neighboring
lines in the same and the adjacent layers above and below. These expressions are simple, and
the calculated results are within 10% of Ansys Q3D extracted values.
Through silicon via (TSV) is one of the key components of the emerging 3D ICs.
However, increasing number of TSVs in smaller silicon area leads to some severe negative
impacts on the performance of the 3D IC. Growing signal integrity issues in TSVs is one of
the major challenges of 3D integration. In this paper, different materials for the cores of the
vias and the interposers are investigated to find the best possible combination that can reduce
crosstalk and other losses like return loss and insertion loss in the TSVs. We have explored
glass and silicon as interposer materials. The simulation results indicate that glass is the best
option as interposer material although silicon interposer has some distinct advantages. For
via cores three materials - copper (Cu), tungsten (W) and Cu-W bimetal are considered. From
the analysis it can concluded that W would be better for high frequency applications due to
lower transmission coefficient. Cu offers higher conductivity, but it has larger thermal
expansion coefficient mismatch with silicon. The performance of Cu-W bimetal via would be
in between Cu and W. However, W has a thermal expansion coefficient close to silicon.
Therefore, bimetal Cu-W based TSV with W as the outer layer would be a suitable option for
high frequency 3D IC. Here, we performed the analysis in terms of return loss, transmission
coefficient and crosstalk in the vias.
Signal speed in current digital systems depends mainly on the delay of interconnects.
To overcome this delay problem and keep up with Moore’s law, 3D integrated circuit
(vertical integration of multiple dies) with through-silicon via (TSV) has been introduced to
ensure much smaller interconnect lengths, and lower delay and power consumption
compared to conventional 2D IC technology. Like 2D circuit, the estimation of 3D circuit
performance depends on different electrical parameters (capacitance, resistance, inductance)
of the TSV. So, accurate modeling of the electrical parameters of the TSV is essential for the
design and analysis of 3D ICs. We propose a set of new models to estimate the capacitance,
resistance, and inductance of a Cu-filled TSV. The proposed analytical models are derived
from the physical shape and the size of the TSV. The modeling approach is comprehensive
and includes both the cylindrical and tapered TSVs as well as the bumps.
On-chip integration of inductors has always been very challenging. However, for sub-
14nm on-chip applications, large area overhead imposed by the on-chip capacitors and
inductors has become a more severe concern. To overcome this issue and ensure power
integrity, a novel 3D Through-Silicon-Via (TSV) based inductor design is presented. The
proposed TSV based inductor has the potential to achieve both high density and high
performance. A new design of a Voltage Controlled Oscillator (VCO) utilizing the TSV
based inductor is also presented. The implementation of the VCO is intended to study the
feasibility, performance, and real-world application of the proposed TSV based inductor.Introduction -- Background of capacitance modeling of on-chip interconnect -- Accurate modeling of interconnect capacitance in multilevel interconnect structures for sub 22nm technology -- Analysis of different materials and structures for through silicon via and through glass via in 3D integrated circuits -- Impacts of different shapes of through-silicon-via core on 3D IC performance -- Accurate electrical modeling of cu-filled through-silicon-via (TSV) -- Design and characterize TSV based inductor for high frequency voltage-controlled oscillator design -- Conclusion and future wor
Carbon nanotubes as interconnect for next generation network on chip
Multi-core processors provide better performance when compared with their single-core equivalent. Recently, Networks-on-Chip (NoC) have emerged as a communication methodology for multi core chips. Network-on-Chip uses packet based communication for establishing a communication path between multiple cores connected via interconnects. Clock frequency, energy consumption and chip size are largely determined by these interconnects. According to the International Technology Roadmap for Semiconductors (ITRS), in the next five years up to 80% of microprocessor power will be consumed by interconnects. In the sub 100nm scaling range, interconnect behavior limits the performance and correctness of VLSI systems. The performance of copper interconnects tend to get reduced in the sub 100nm range and hence we need to examine other interconnect options. Single Wall Carbon Nanotubes exhibit better performance in sub 100nm processing technology due to their very large current carrying capacity and large electron mean free paths. This work suggests using Single Wall Carbon Nanotubes (SWCNT) as interconnects for Networks-on-Chip as they consume less energy and gives more throughput and bandwidth when compared with traditional Copper wires
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Field theoretic analysis of a class of planar microwave and opto-electronic structures
With increasing operating frequencies in CMOS RF/microwave integrated circuits,
the performance of on-chip interconnects is becoming significantly affected by the lossy
substrate. It is the purpose of the first part of this thesis to develop a rigorous field
theoretic analysis approach for efficient characterization of single and multiple coupled
interconnects on silicon substrate, which is applicable over a wide range of substrate
resistivities. The frequency-dependent transmission line parameters of a microstrip on
silicon are determined by a new formulation based on a quasi-electrostatic and quasi-magnetostatic
spectral domain approach. It is demonstrated that this new quasi-static
formulation provides the complete frequency-dependent interconnect characteristics for
all three major transmission line modes of operation. In particular, it is shown that in the
case of heavily doped CMOS substrates, the distributed series inductance and series
resistance parameters are significantly affected by the presence of longitudinal substrate
currents giving rise to the substrate skin-effect. The method is further extended to
multiple coupled single and multi-level interconnect structures with ground plane and
multiple coupled co-planar stripline structures without ground plane. The finite conductor
thickness is taken into account in terms of a stacked conductor model. The new quasi-static
approach is validated by comparison with results obtained with a full-wave spectral
domain method and the commercial planar full-wave electromagnetic field solver
HP/Momentum®, as well as published simulation and measurement data.
In the second part of this thesis, coupled planar optical interconnect structures are
investigated based on a rigorous field theoretic analysis combined with an application of
the normal mode theory for coupled transmission lines. A new transfer matrix description
for a general optical directional coupler is presented. Based on this transfer matrix
formulation, the wavelength-dependent characteristics of multi-section optical filters
consisting of cascaded asymmetric optical directional coupler sections are investigated. It
is shown that by varying the asymmetry factors of the cascaded coupled waveguide
sections, optical wavelength filters with different passband properties can be achieved
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