A substrate noise coupling model for lightly doped CMOS processes

This thesis presents a design-oriented model for lightly doped CMOS substrates. The model predicts the substrate noise coupling between noisy digital and sensitive analog blocks in the early stages of the design. The model scales with the size and separation of these blocks and it is validated with device simulations and with measurements on two different test chips. The effectiveness of different isolation techniques is investigated for lightly doped CMOS processes using device simulations and it is shown that P+ guard rings offer the best isolation, supppressing the noise by as much as 45dB when the guard rings are within a few microns of the noise injector. Finally, the model is used to predict noise coupling between an inverter and an amplifier, with both circuit simulations and measurements on a chip fabricated in the TSMC 0.35Ecm CMOS process

An efficient modeling approach for substrate noise coupling analysis with multiple contacts in heavily doped CMOS processes

A computationally efficient and accurate substrate noise coupling model for multiple contacts in heavily doped CMOS processes is presented and validated with simulations and experimental data. The model is based on Z parameters that are scalable with contact separation and size. This results in fast extraction of substrate resistances for large circuit examples. The Z-parameter model can be readily extracted from three dimensional simulations or measured data. Extensions of the model to lightly doped substrates are also presented. Several examples demonstrate that this approach can be orders of magnitude faster than currently available techniques for substrate resistance extraction. The computed substrate resistances are in close agreement with the numerical simulations, with a maximum error less than 10%

Characterization and Modeling of High Power Microwave Effects in CMOS Microelectronics

The intentional use of high power microwave (HPM) signals to disrupt microelectronic systems is a substantial threat to vital infrastructure. Conventional methods to assess HPM threats involve empirical testing of electronic equipment, which provides no insight into fundamental mechanisms of HPM induced upset. The work presented in this dissertation is part of a broad effort to develop more effective means for HPM threat assessment. Comprehensive experimental evaluation of CMOS digital electronics was performed to provide critical information of the elementary mechanisms that govern the dynamics of HPM effects. Results show that electrostatic discharge (ESD) protection devices play a significant role in the behavior of circuits irradiated by HPM pulses. The PN junctions of the ESD protection devices distort HPM waveforms producing DC voltages at the input of the core logic elements, which produces output bit errors and abnormal circuit power dissipation. The dynamic capacitance of these devices combines with linear parasitic elements to create resonant structures that produce nonlinear circuit dynamics such as spurious oscillations. The insight into the fundamental mechanisms this research has revealed will contribute substantially to the broader effort aimed at identifying and mitigating susceptibilities in critical systems. Also presented in this work is a modeling technique based on scalable analytical circuit models that accounts for the non-quasi-static behavior of the ESD protection PN junctions. The results of circuit simulations employing these device models are in excellent agreement with experimental measurements, and are capable of predicting the threshold of effect for HPM driven non-linear circuit dynamics. For the first time, a deterministic method of evaluating HPM effects based on physical, scalable device parameters has been demonstrated. The modeling presented in this dissertation can be easily integrated into design cycles and will greatly aid the development of electronic systems with improved HPM immunity

Development and Validation of a Microcontroller Model for EMC

Models of integrated circuits (ICs) allow printed circuit board (PCB) developers to predict radiated and conducted emissions early in board development and allow IC manufactures insight into how to build their ICs better for electromagnetic compatibility (EMC). A model of the power delivery network, similar to the ICEM or LECCS model, was developed for a microcontroller running a typical program and used to predict the noise voltage between the power and return planes of a PCB. The IC and package model was generated using the Apache tool suite. A model of the PCB was created using an electromagnetic cavity model and lumped-element models of components on the board. Values of predicted and measured impedance looking into the IC and PCB matched within a few dB from a few 10s of MHz up to 1 GHz. Measured and predicted values of noise voltage matched within about 6 dB at clock harmonics up to 600-700 MHz

Predictive methodologies for substrate parasitic extraction and modeling in heavily doped CMOS substrates

This thesis presents an automated methodology to calibrate the substrate profile for accurate prediction of substrate parasitics using Green's function based extractors. The technique requires fabrication of only a few test structures and results in an accurate three layered approximation of a heavily doped epitaxial silicon substrate. The obtained substrate resistances are accurate to about 10% of measurements. Advantages and limitations of several common measurement techniques used to measure substrate z-parameters and resistances are discussed. A new and accurate z-parameter based macro-model has been developed that can be used up to a few GHz for P⁺ for contacts that are as close as 2μm. This enhanced model also addresses the limitations of previous models with regards to implementation aspects and ease of integration in a CAD framework. Limitations of this modeling approach have been investigated. The calibration methodology can be used along with the scalable macromodel for a qualitative pre-design and pre-layout estimation of the digital switching noise that couples though the substrate to sensitive analog/RF circuits

Fast algorithms for ill-conditioned dense matrix problems in VLSI interconnect and substrate modeling

Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 1998.Includes bibliographical references (leaves 131-135).by Mike Chuan Chou.Ph.D

On the suitability and development of layout templates for analog layout reuse and layout-aware synthesis

Accelerating the synthesis of increasingly complex analog integrated circuits is key to bridge the widening gap between what we can integrate and what we can design while meeting ever-tightening time-to-market constraints. It is a well-known fact in the semiconductor industry that such goal can only be attained by means of adequate CAD methodologies, techniques, and accompanying tools. This is particularly important in analog physical synthesis (a.k.a. layout generation), where large sensitivities of the circuit performances to the many subtle details of layout implementation (device matching, loading and coupling effects, reliability, and area features are of utmost importance to analog designers), render complete automation a truly challenging task. To approach the problem, two directions have been traditionally considered, knowledge-based and optimization-based, both with their own pros and cons. Besides, recently reported solutions oriented to speed up the overall design flow by means of reuse-based practices or by cutting off time-consuming, error-prone spins between electrical and layout synthesis (a technique known as layout-aware synthesis), rely on a outstandingly rapid yet efficient layout generation method. This paper analyses the suitability of procedural layout generation based on templates (a knowledge-based approach) by examining the requirements that both layout reuse and layout-aware solutions impose, and how layout templates face them. The ability to capture the know-how of experienced layout designers and the turnaround times for layout instancing are considered main comparative aspects in relation to other layout generation approaches. A discussion on the benefit-cost trade-off of using layout templates is also included. In addition to this analysis, the paper delves deeper into systematic techniques to develop fully reusable layout templates for analog circuits, either for a change of the circuit sizing (i.e., layout retargeting) or a change of the fabrication process (i.e., layout migration). Several examples implemented with the Cadence's Virtuoso tool suite are provided as demonstration of the paper's contributions.Ministerio de Educación y Ciencia TEC2004-0175

Automatic synthesis of analog layout : a survey

A review of recent research in the automatic synthesis of physical geometry for analog integrated circuits is presented. On introduction, an explanation of the difficulties involved in analog layout as opposed to digital layout is covered. Review of the literature then follows. Emphasis is placed on the exposition of general methods for addressing problems specific to analog layout, with the details of specific systems only being given when they surve to illustrate these methods well. The conclusion discusses problems remaining and offers a prediction as to how technology will evolve to solve them. It is argued that although progress has been and will continue to be made in the automation of analog IC layout, due to fundamental differences in the nature of analog IC design as opposed to digital design, it should not be expected that the level of automation of the former will reach that of the latter any time soon

Substrate coupling macromodel for lightly doped CMOS processes

A scalable macromodel for substrate noise coupling in lightly doped substrates with and without a buried layer has been developed. This model is based on Z-parameters and is scalable with contact size and separation. This model requires process dependent parameters that can be extracted easily from a small number of device simulations or measurements. Once these parameters are known, the model can be used for any spacing between the injecting and sensing contacts and for different contact geometries. The model is validated with measurements for a lightly doped substrate with a buried layer and predicts the substrate resistance values to within 12%. The substrate resistances obtained using the model are also in close agreement with the three-dimensional simulations for a lightly doped substrate