This thesis presents a design-oriented model for lightly doped CMOS substrates. The model predicts the substrate noise coupling between noisy digital and sensitive analog blocks in the early stages of the design. The model scales with the size and separation of these blocks and it is validated with device simulations and with measurements on two different test chips. The effectiveness of different isolation techniques is investigated for lightly doped CMOS processes using device simulations and it is shown that P+ guard rings offer the best isolation, supppressing the noise by as much as 45dB when the guard rings are within a few microns
of the noise injector. Finally, the model is used to predict noise coupling between an inverter and an amplifier, with both circuit simulations and measurements on a chip fabricated in the TSMC 0.35Ecm CMOS process
