Oscillation-Based Test Structure and Method for OTA-C Filters

“This material is presented to ensure timely dissemination of scholarly and technical work. Copyright and all rights therein are retained by authors or by other copyright holders. All persons copying this information are expected to adhere to the terms and constraints invoked by each author's copyright. In most cases, these works may not be reposted without the explicit permission of the copyright holder." “Copyright IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE.”This paper describes a design for testability technique for operational transconductance amplifier and capacitor filters using an oscillation-based test topology. The oscillation-based test structure is a vectorless output test strategy easily extendable to built-in self-test. The proposed methodology converts filter under test into a quadrature oscillator using very simple techniques and measures the output frequency. The oscillation frequency may be considered as a digital signal and it can be evaluated using digital circuitry therefore the test time is very small. These characteristics imply that the proposed method is very suitable for catastrophic and parametric faults testing and also effective in detecting single and multiple faults. The validity of the proposed method has been verified using comparison between faulty and fault-free simulation results of two integrator loop and Tow-Thomas filters. Simulation results in 0.25 mum CMOS technology show that the proposed oscillation-based test strategy for OTA-C filters has 87% fault coverage and with a minimum number of extra components, requires a negligible area overhead

Oscillation-based Test Method for Continuous-time OTA-C Filters

“This material is presented to ensure timely dissemination of scholarly and technical work. Copyright and all rights therein are retained by authors or by other copyright holders. All persons copying this information are expected to adhere to the terms and constraints invoked by each author's copyright. In most cases, these works may not be reposted without the explicit permission of the copyright holder." “Copyright IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE.”Design for testability technique using oscillation-based test topology for KHN OTA-C filters is proposed. The oscillation-based test structure is a vectorless output test strategy easily extendable to built-in self-test. During test mode, the filter under test is converted into an oscillator by establishing the oscillation condition in its transfer function. The oscillator frequency can be measured using digital circuitry and deviations from the cut-off frequency indicate the faulty behaviour of the filter. The proposed method is suitable for both catastrophic and parametric fault diagnosis as well as effective in detecting single and multiple faults. The validity of the proposed method has been verified using comparison between faulty and fault-free simulation results of KHN OTA-C filter. Simulation results in 0.25mum CMOS technology show that the proposed oscillation-based test strategy has 84% fault coverage and with a minimum number of extra components, requires a negligible area overhead.Final Published versio

Analog Defect Injection and Fault Simulation Techniques: A Systematic Literature Review

Since the last century, the exponential growth of the semiconductor industry has led to the creation of tiny and complex integrated circuits, e.g., sensors, actuators, and smart power. Innovative techniques are needed to ensure the correct functionality of analog devices that are ubiquitous in every smart system. The ISO 26262 standard for functional safety in the automotive context specifies that fault injection is necessary to validate all electronic devices. For decades, standardization of defect modeling and injection mainly focused on digital circuits and, in a minor part, on analog ones. An initial attempt is being made with the IEEE P2427 draft standard that started to give a structured and formal organization to the analog testing field. Various methods have been proposed in the literature to speed up the fault simulation of the defect universe for an analog circuit. A more limited number of papers seek to reduce the overall simulation time by reducing the number of defects to be simulated. This literature survey describes the state-of-the-art of analog defect injection and fault simulation methods. The survey is based on the Preferred Reporting Items for Systematic Reviews and Meta-Analyses (PRISMA) methodological flow, allowing for a systematic and complete literature survey. Each selected paper has been categorized and presented to provide an overview of all the available approaches. In addition, the limitations of the various approaches are discussed by showing possible future directions

Fault simulation for structural testing of analogue integrated circuits

In this thesis the ANTICS analogue fault simulation software is described which provides a statistical approach to fault simulation for accurate analogue IC test evaluation. The traditional figure of fault coverage is replaced by the average probability of fault detection. This is later refined by considering the probability of fault occurrence to generate a more realistic, weighted test metric. Two techniques to reduce the fault simulation time are described, both of which show large reductions in simulation time with little loss of accuracy. The final section of the thesis presents an accurate comparison of three test techniques and an evaluation of dynamic supply current monitoring. An increase in fault detection for dynamic supply current monitoring is obtained by removing the DC component of the supply current prior to measurement

Methods for testing of analog circuits

Práce se zabývá metodami pro testování lineárních analogových obvodů v kmitočtové oblasti. Cílem je navrhnout efektivní metody pro automatické generování testovacího plánu. Snížením počtu měření a výpočetní náročnosti lze výrazně snížit náklady za testování. Práce se zabývá multifrekveční parametrickou poruchovou analýzou, která byla plně implementována do programu Matlab. Vhodnou volbou testovacích kmitočtů lze potlačit chyby měření a chyby způsobené výrobními tolerancemi obvodových prvků. Navržené metody pro optimální volbu kmitočtů byly statisticky ověřeny metodou MonteCarlo. Pro zvýšení přesnosti a snížení výpočetní náročnosti poruchové analýzy byly vyvinuty postupy založené na metodě nejmenších čtverců a přibližné symbolické analýze.The thesis deals with methods for testing of linear analog circuits in the frequency domain. The goal is to develop new efficient methods for automatic test plan generation. To reduce test costs a minimum number of measurements as well as less computational demands are the fundamental aims. The thesis is focused on the multi-frequency parametric fault diagnosis which was fully implemented in the Matlab program. The fundamental problem consists in selection of test frequencies which can reduce the influences of measurement errors and errors caused by tolerances of well-working components. The proposed methods for test frequency selection were statistically verified by the MonteCarlo method. To improve the accuracy and reduce the computational complexity of fault diagnosis, the methods based on least-square techniques and approximate symbolic analysis were presented.

Testing microelectronic biofluidic systems

According to the 2005 International Technology Roadmap for Semiconductors, the integration of emerging nondigital CMOS technologies will require radically different test methods, posing a major challenge for designers and test engineers. One such technology is microelectronic fluidic (MEF) arrays, which have rapidly gained importance in many biological, pharmaceutical, and industrial applications. The advantages of these systems, such as operation speed, use of very small amounts of liquid, on-board droplet detection, signal conditioning, and vast digital signal processing, make them very promising. However, testable design of these devices in a mass-production environment is still in its infancy, hampering their low-cost introduction to the market. This article describes analog and digital MEF design and testing method

A collection of fuzzy logic-based tools for the automated design, modelling and test of analog circuits

We have developed a collection of tools for the design, modeling, and test of analog circuits. Sharing a common fuzzy-logic based framework, the tools are part of FASY (Fuzzy-Logic-Based Analog Synthesis), an analog design package developed at the University of Seville. The first tool uses fuzzy logic for topology selection of analog cells. It follows decision rules directly entered by a human expert or automatically generated from its experience with earlier designs. Second, a performance-modeling tool provides a qualitative description of a circuit's behavior. Alternatively, it can use a learning process to accurately model circuit performance. Finally, an analog testing tool uses a fuzzy-neuron classifier to detect and classify faults in analog circuits

Design for testability of high-order OTA-C filters

Copyright © 2016 John Wiley & Sons, Ltd.A study of oscillation-based test for high-order Operational Transconductance Amplifier-C (OTA-C) filters is presented. The method is based on partition of a high-order filter into second-order filter functions. The opening Q-loop and adding positive feedback techniques are developed to convert the second-order filter section into a quadrature oscillator. These techniques are based on an open-loop configuration and an additional positive feedback configuration. Implementation of the two testability design methods for nth-order cascade, IFLF and leapfrog (LF) filters is presented, and the area overhead of the modified circuits is also discussed. The performances of the presented techniques are investigated. Fourth-order cascade, inverse follow-the-leader feedback (IFLF) and LF OTA-C filters were designed and simulated for analysis of fault coverage using the adding positive feedback method based on an analogue multiplexer. Simulation results show that the oscillation-based test method using positive feedback provides high fault coverage of around 97%, 96% and 95% for the cascade, IFLF and LF OTA-C filters, respectively. Copyright ÂPeer reviewe

A design for testability study on a high performance automatic gain control circuit.

A comprehensive testability study on a commercial automatic gain control circuit is presented which aims to identify design for testability (DfT) modifications to both reduce production test cost and improve test quality. A fault simulation strategy based on layout extracted faults has been used to support the study. The paper proposes a number of DfT modifications at the layout, schematic and system levels together with testability. Guidelines that may well have generic applicability. Proposals for using the modifications to achieve partial self test are made and estimates of achieved fault coverage and quality levels presente

Symbolic tolerance and sensitivity analysis of large scale electronic circuits

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