Scalable diversified antirandom test pattern generation with improved fault coverage for black-box circuit testing

Pseudorandom testing is incapable of utilizing the success rate of preceding test patterns while generating subsequent test patterns. Many redundant test patterns have been generated that increase the test length without any significant increase in the fault coverage. An extension to pseudorandom testing is Antirandom that induces divergent patterns by maximizing the Total Hamming Distance (THD) and Total Cartesian Distance (TCD) of every subsequent test pattern. However, the Antirandom test sequence generation algorithm is prone to unsystematic selection when more than one patterns possess maximum THD and TCD. As a result, diversity among test sequences is compromised, lowering the fault coverage. Therefore, this thesis analyses the effect of Hamming distance in vertical as well as horizontal dimension to enhance diversity among test patterns. First contribution of this thesis is the proposal of a Diverse Antirandom (DAR) test pattern generation algorithm. DAR employs Horizontal Total Hamming Distance (HTHD) along with THD and TCD for diversity enhancement among test patterns as maximum distance test pattern generation. The HTHD and TCD are used as distance metrics that increase computational complexity in divergent test sequence generation. Therefore, the second contribution of this thesis is the proposal of tree traversal search method to maximize diversity among test patterns. The proposed method uses bits mutation of a temporary test pattern following a path leading towards maximization of TCD. Results of fault simulations on benchmark circuits have shown that DAR significantly improves the fault coverage up to 18.3% as compared to Antirandom. Moreover, the computational complexity of Antirandom is reduced from exponential O(2n) to linear O(n). Next, the DARalgorithm is modified to ease hardware implementation for on-chip test generation. Therefore, the third contribution of this thesis is the design of a hardware-oriented DAR (HODA) test pattern generator architecture as an alternative to linear feedback shift register (LFSR) that consists of large number of memory elements. Parallel concatenation of the HODA architecture is designed to reduce the number of memory elements by implementing bit slicing architecture. It has been proven through simulation that the proposed architecture has increased fault coverage up to 66% and a reduction of 46.59% gate count compared to the LFSR. Consequently, this thesis presents uniform and scalable test pattern generator architecture for built-in self-test (BIST) applications and solution to maximum distance test pattern generation for high fault coverage in black-box environment

Test vectors reductoin for integrated circuit testing using horizontal hamming distance

In testing digital combinational logic for stuck-at faults, it is required to determine the most appropriate test sequence needed to detect the required number of possible faults. The exhaustive test pattern generation method is the simplest approach to implement as it produces test patterns consisting of all possible input combinations of the circuit under test. However, a consequence of this approach is that it results in a large test set when the number of circuit inputs is large. This can take an unnecessarily long time to apply on the circuit under test as during the test process, only a small fraction of all possible test vectors is actually required to produce high percentage of fault coverage. As an alternative, random test pattern generation applies a random set of test patterns which can be used to reduce the number of test patterns compared to exhaustive test. However, both test pattern generation approaches generate unnecessary test vectors to apply to the circuit as multiple patterns typically detect the same fault. Antirandom testing on the other hand ensures that the identified test vectors to use do not detect the same fault by introducing the concept of Hamming distance between test vectors and this distance is be maximized. This results in a reduction in the number of required test vectors when compared to an exhaustive test. However, the algorithm for Antirandom test vector generation is computation intensive and vague in its definition when there are more than one possible next test vectors. In this study, efficient calculation of Hamming distance has been proposed, moreover the choice of the next test vector is addressed by using the proposed Horizontal Hamming distance method which has not yet been explored. The approach effectively detects faults at a much faster rate and produces a much higher fault coverage than the existing Antirandom method

A Total Self Checking Comparator Implementable on FPGAS Using Bist Technology

an integrated circuits (IC) "manufacturing tests" may be made easier to administer with the use of design for testability (DFT). Integrated circuits' embedded memory tests make use of the TSC (TSC) approach. We have shown the TSC method and several algorithms used in TSC for the purpose of testing embedded memory in this article. An address generator, controller, comparator, and memory are the four main components of this kind of memory TSC technology. This paper details the three memory TSC controller implementation techniques. The memory TSC controller is modelled in Verilog HDL, and its accuracy is checked using the RTL compiler before synthesis. Here we provide a way to build TSC comparators for TSC systems that may be implemented on FPGAs—totally self-checking (TSC) systems—that can be used online. By directly measuring the output of each lookup table (LUT), this approach may be utilised to do comprehensive online diagnostics of all LUTs. This entails mapping the basic components of the comparator with a limited number of test patterns. With our technique, we can achieve exhaustive diagnosis with a small number of test patterns on the order of n [O(n)] (where n is the input number to the comparator) while yet covering all bases 100% of the time, even if we are just aware of the LUT's specs and not its exact structure. For systems that need absolute reliability, FPGAs will be a perfect fit. Our experiment also included a single-event upset (SEU) induced by neutron radiation to validate the soft error rate (SER) in a field-programmable gate array (FPGA) based on static random-access memory (SRAM)

Test and security in a System-on-Chip environment

This dissertation outlines new approaches for test and security in a System-on-Chip (SoC) environment. A methodology is proposed for designing a single test access mechanism (TAM) architecture on each die with a "bandwidth adapter" that allows it to be efficiently used for multiple different test data bandwidths in three-dimensional integrated circuits (3D-IC) using through-silicon vias (TSVs). In this way, a single test architecture can be re-used for pre-bond, partial stack, and post-bond testing while minimizing test time across all phases of test. Unlike previous approaches, this methodology does not need multiple TAM architectures or reconfigurable wrappers in order to be efficient when the test data bandwidth changes. In industry, sequential linear decompression is widely used to reduce data and bandwidth requirements. A new scheme using a multiple polynomial linear feedback shift register (LFSR) with rotating polynomial is proposed here to increase encoding flexibility resulting in higher compression ratios. An algorithm is described to assign test cubes to polynomials in a way that enhances encoding efficiency. For hardware security, a new attack strategy against logic obfuscation is described here. It is based on applying brute force iteratively to each logic cone one at a time and is shown to significantly reduce the number of brute force key combinations that need to be tried by an attacker. It is shown that inserting key gates based on MUXes is an effective approach to increase security against this type of attack. In data security for hardware, existing techniques for computing with encrypted operands are either prohibitively expense (e.g., fully homomorphic encryption) or only work for special cases (e.g., linear circuits). A lightweight scheme implemented at the gate-level is proposed for computing with noise-obfuscated data. By carefully selecting internal locations for noise cancellation in arbitrary logic circuits, the overhead can be greatly minimized. One important application of the proposed scheme is for protecting data inside a computing unit obtained from a third party IP provider where a hidden backdoor access mechanism or hardware Trojan could be maliciously inserted.Electrical and Computer Engineerin

An approach to Measure Transition Density of Binary Sequences for X-filling based Test Pattern Generator in Scan based Design

Switching activity and Transition density computation is an essential stage for dynamic power estimation and testing time reduction. The study of switching activity, transition densities and weighted switching activities of pseudo random binary sequences generated by Linear Feedback shift registers and Feed Forward shift registers plays a crucial role in design approaches of Built-In Self Test, cryptosystems, secure scan designs and other applications. This paper proposed an approach to find transition densities, which plays an important role in choosing of test pattern generator We have analyze conventional and proposed designs using our approache, This work also describes the testing time of benchmark circuits. The outcome of this paper is presented in the form of algorithm, theorems with proofs and analyses table which strongly support the same. The proposed algorithm reduces switching activity and testing time up to 51.56% and 84.61% respectively

Embedding deterministic patterns in partial pseudo-exhaustive test

The topic of this thesis is related to testing of very large scale integration circuits. The thesis presents the idea of optimizing mixed-mode built-in self-test (BIST) scheme. Mixed-mode BIST consists of two phases. The first phase is pseudo-random testing or partial pseudo-exhaustive testing (P-PET). For the faults not detected by the first phase, deterministic test patterns are generated and applied in the second phase. Hence, the defect coverage of the first phase influences the number of patterns to be generated and stored. The advantages of P-PET in comparison with usual pseudo-random test are in obtaining higher fault coverage and reducing the number of deterministic patterns in the second phase of mixed-mode BIST. Test pattern generation for P-PET is achieved by selecting characteristic polynomials of multiple-polynomial linear feedback shift register (MP-LFSR). In this thesis, the mixed-mode BIST scheme with P-PET in the first phase is further improved in terms of the fault coverage of the first phase. This is achieved by optimization of polynomial selection of P-PET. In usual mixed-mode BIST, the set of undetected by the first phase faults is handled in the second phase by generating deterministic test patterns for them. The method in the thesis is based on consideration of these patterns during polynomial selection. In other words, we are embedding deterministic test patterns in P-PET. In order to solve the problem, the algorithm for the selection of characteristic polynomials covering the pre-generated patterns is developed. The advantages of the proposed approach in terms of the defect coverage and the number of faults left after the first phase are presented using contemporary industrial circuits. A comparison with usual pseudo-random testing is also performed. The results prove the benefits of P-PET with embedded test patterns in terms of the fault coverage, while maintaining comparable test length and time

Testing for delay defects utilizing test data compression techniques

textAs technology shrinks new types of defects are being discovered and new fault models are being created for those defects. Transition delay and path delay fault models are two such models that have been created, but they still fall short in that they are unable to obtain a high test coverage of smaller delay defects; these defects can cause functional behavior to fail and also indicate potential reliability issues. The first part of this dissertation addresses these problems by presenting an enhanced timing-based delay fault testing technique that incorporates the use of standard delay ATPG, along with timing information gathered from standard static timing analysis. Utilizing delay fault patterns typically increases the test data volume by 3-5X when compared to stuck-at patterns. Combined with the increase in test data volume associated with the increase in gate count that typically accompanies the miniaturization of technology, this adds up to a very large increase in test data volume that directly affect test time and thus the manufacturing cost. The second part of this dissertation presents a technique for improving test compression and reducing test data volume by using multiple expansion ratios while determining the configuration of the scan chains for each of the expansion ratios using a dependency analysis procedure that accounts for structural dependencies as well as free variable dependencies to improve the probability of detecting faults. Finally, this dissertation addresses the problem of unknown values (X’s) in the output response data corrupting the data and degrading the performance of the output response compactor and thus the overall amount of test compression. Four techniques are presented that focus on handling response data with large percentages of X’s. The first uses X-canceling MISR architecture that is based on deterministically observing scan cells, and the second is a hybrid approach that combines a simple X-masking scheme with the X-canceling MISR for further gains in test compression. The third and fourth techniques revolve around reiterative LFSR X-masking, which take advantage of LFSR-encoded masks that can be reused for multiple scan slices in novel ways.Electrical and Computer Engineerin

Testing PUF-Based Secure Key Storage Circuits

Abstract-Design for test is an integral part of any VLSI chip. However, for secure systems extra precautions have to be taken to prevent that the test circuitry could reveal secret information. This paper addresses secure test for Physical Unclonable Function based systems. In particular it provides the testability analysis and a secure Built-In Self-Test (BIST) solution for Fuzzy Extractor (FE) which is the main component of PUF-based systems. The scheme targets high stuck-at-fault (SAF) coverage by performing scan-chain free functional testing, to prevent scan-chain abuse for attacks. The scheme reuses existing FE sub-blocks (for pattern generation and compression) to minimize the area overhead. The scheme is integrated in FE design and simulated; the results show that a SAF fault coverage of 95.1% can be realized with no more than 50k clock cycles at the cost of a negligible area overhead of only 2.2%. Higher fault coverage is possible to realize at extra cost