An Energy-Efficient Design Paradigm for a Memory Cell Based on Novel Nanoelectromechanical Switches

In this chapter, we explain NEMsCAM cell, a new content-addressable memory (CAM) cell, which is designed based on both CMOS technologies and nanoelectromechanical (NEM) switches. The memory part of NEMsCAM is designed with two complementary nonvolatile NEM switches and located on top of the CMOS-based comparison component. As a use case, we evaluate first-level instruction and data translation lookaside buffers (TLBs) with 16 nm CMOS technology at 2 GHz. The simulation results demonstrate that the NEMsCAM TLB reduces the energy consumption per search operation (by 27%), standby mode (by 53.9%), write operation (by 41.9%), and the area (by 40.5%) compared to a CMOS-only TLB with minimal performance overhead

Performance Analysis of Nanoelectromechanical Relay-Based Field-Programmable Gate Arrays

The energy consumption of field-programmable gate arrays (FPGA) is dominated by leakage currents and dynamic energy associated with programmable interconnect. An FPGA built entirely from nanoelectromechanical (NEM) relays can effectively eliminate leakage energy losses, reduce the interconnect dynamic energy, operate at temperatures &gt;225 °C and tolerate radiation doses in excess of 100 Mrad, while hybrid FPGAs comprising both complementary metal-oxide-semiconductor (CMOS) transistors and NEM relays (NEM-CMOS) have the potential to realize improvements in performance and energy efficiency. Large-scale integration of NEM relays, however, poses a significant engineering challenge due to the presence of moving parts. We discuss the design of FPGAs utilizing NEM relays based on a heterogeneous 3-D integration scheme, and carry out a scaling study to quantify key metrics related to performance and energy efficiency in both NEM-only and NEM-CMOS FPGAs. We show how the integration scheme has a profound effect on these metrics by changing the length of global wires. The scaling regime beyond which net performance and energy benefits is seen in NEM-CMOS over a baseline 90 nm CMOS technology is defined by an effective relay beam length of 0.5 μm , on-resistance of 200 kΩ , and a via pitch of 0.4 μm , all achievable with existing process technology. For ultra-low energy applications that are not performance critical, NEM-only FPGAs can provide close to 15× improvement in energy efficiency.QC 20180412</p

NEMsCAM: A novel CAM cell based on nano-electro-mechanical switch and CMOS for energy efficient TLBs

In this paper we propose a novel Content Addressable Memory (CAM) cell, NEMsCAM, based on both Nano-electro-mechanical (NEM) switches and CMOS technologies. The memory component of the proposed CAM cell is designed with two complementary non-volatile NEM switches and located on top of the CMOS-based comparison component. As a use case for the NEMsCAM cell, we design first-level data and instruction Translation Lookaside Buffers (TLBs) with 16nm CMOS technology at 2GHz. The simulations show that the NEMsCAM TLB reduces the energy consumption per search operation (by 27%), write operation (by 41.9%) and standby mode (by 53.9%), and the area (by 40.5%) compared to a CMOS-only TLB with minimal performance overhead.We thank all anonymous reviewers for their insightful comments. This work is supported in part by the European Union (FEDER funds) under contract TIN2012-34557, and the European Union’s Seventh Framework Programme (FP7/2007-2013) under the ParaDIME project (GA no. 318693)Postprint (author's final draft

Nanoelectromechanical relay without pull-in instability for high-temperature non-volatile memory

Emerging applications such as the Internet-of-Things and more-electric aircraft require electronics with integrated data storage that can operate in extreme temperatures with high energy efficiency. As transistor leakage current increases with temperature, nanoelectromechanical relays have emerged as a promising alternative. However, a reliable and scalable non-volatile relay that retains its state when powered off has not been demonstrated. Part of the challenge is electromechanical pull-in instability, causing the beam to snap in after traversing a section of the airgap. Here we demonstrate an electrostatically actuated nanoelectromechanical relay that eliminates electromechanical pull-in instability without restricting the dynamic range of motion. It has several advantages over conventional electrostatic relays, including low actuation voltages without extreme reduction in critical dimensions and near constant actuation airgap while the device moves, for improved electrostatic control. With this nanoelectromechanical relay we demonstrate the first high-temperature non-volatile relay operation, with over 40 non-volatile cycles at 200 ∘C

Nano-crystalline graphite for reliability improvement in MEM relay contacts

Micro- and Nano-electromechanical (MEM/NEM) relays can operate with zero-leakage at far higher temperatures and levels of radiation than transistors, but have poor reliability. This work demonstrates improvement in reliability of MEM relays using nano-crystalline graphite (NCG)-coated contact surfaces. The high stability of NCG in ambient air, along with its low surface energy, appears to make it an ideal contact material. NCG-coated relays achieved over 2.8 million fast, hot-switching cycles with a drain current of at least 5 μA and on-resistance under 17 kΩ, in ambient air. The relays also were tested in slow, hot-switching cycles designed to increase the electrical stress on the contact, and consistently achieved on-currents up to 50 μA or the imposed current limit without failure. The eventual cause of failure appeared to be mechanical stress on the NCG layer over repeated cycling causing degradation. Increasing the layer thickness is expected to further improve the contact reliability. The relays are scalable and can be used as micro- or nano-scale switches in electronic components designed for very high temperatures and levels of radiation.</p

DEVELOPMENT OF NANO/MICROELECTROMECHANICAL SYSTEM (N/MEMS) SWITCHES

Ph.DDOCTOR OF PHILOSOPH

Doctor of Philosophy

dissertationThis dissertation describes the design, fabrication, testing, reliability, and harsh environment performance of single-device Micro-electro-mechanical-system (MEMS)- based digital logic gates, such as XOR and AND, for applications in ultra-low-power computation in unforgiving settings such as high ionizing radiation and high temperatures. Within the scope of this dissertation are several significant contributions. First, this work was the first ever to report the evolution in logic design architecture from a CMOS-paradigm to a MEMS architecture utilizing a single functional device per logic, as opposed to multiple relays per logic. This novel approach reduces the number of devices needed to implement a logic function by approximately 10X, leading to better reliability, yield, speed, and overall better characteristics (subthreshold characteristics, smaller turn-on/off voltage variations, etc.) and it simplifies implementation of MEMSbased circuits. The logic gates illustrate ~1.5V turn-on voltage at 5MHz with >109 cycles of reliable operations and low operational power consumption (leakage current and power <10-9A, <1^W). Second, this work is the first ever to report an intensive study on the cycle-bycycle evolution of contact resistance (Rc) up to 100,000 cycles, on materials such as, Ir, Pt, W, Ni, Cr, Ti, Cu, Al, and graphite, which are materials commonly used in MEMS switches. Adhesion forces between contacts were also studied using a contact-modeAFM, force vs. displacement, experiment. Results show that materials with high Young's modulus, high melting temperatures, and high density show low initial contact resistances and low adhesion forces (such as Ir, Pt, and W). Third, the devices were interrogated separately in harsh environments where they were exposed to high doses of ionizing radiation (90kW) in a nuclear reactor for a prolonged time (120 min) and, separately, at high temperatures (409K). Here, results show that solid-state devices begin to deteriorate almost immediately to a point where their gate can no longer control the drain-to-source current, whereas MEMS switches survive such ionizing radiation and temperatures portraying clear ON and OFF states for far longer. In terms of the applications empowered and the breadth of topics covered to accomplish these results, the work presented here demonstrates significant contributions to an important and developing branch of engineering

Non-invasive power gating techniques for bursty computation workloads using micro-electro-mechanical relays

PhD ThesisElectrostatically-actuated Micro-Electro-Mechanical/Nano-Electro- Mechanical (MEM/NEM) relays are promising devices overcoming the energy-efficiency limitations of CMOS transistors. Many exploratory research projects are currently under way investigating the mechanical, electrical and logical characteristics of MEM/NEM relays. One particular issue that this work addresses is the need for a scalable and accurate physical model of the MEM/NEM switches that can be plugged into the standard EDA software. The existing models are accurate and detailed but they suffer from the convergence problem. This problem requires finding ad-hoc workarounds and significantly impacts the designer’s productivity. In this thesis we propose a new simplified Verilog-AMS model. To test scalability of the proposed model we cross-checked it against our analysis of a range of benchmark circuits. Results show that, compared to standard models, the proposed model is sufficiently accurate with an average of 6% error and can handle larger designs without divergence. This thesis also investigates the modelling, designing and optimization of various MEM/NEM switches using 3D Finite Element Analysis (FEA) performed by the COMSOL multiphysics simulation tool. An extensive parametric sweep simulation is performed to study the energy-latency trade-offs of MEM/NEM relays. To accurately simulate MEMS/NEMS-based digital circuits, a Verilog-AMS model is proposed based on the evaluated parameters obtained from the multiphysics simulation tool. This allows an accurate calibration of the MEM/NEM relays with a significant reduction in simulation speed compared to that of 3D FEA exercised on COMSOL tool. The effectiveness of two power gating approaches in asynchronous micropipelines is also investigated using MEM/NEM switches and sleep transistors in reducing idle power dissipation with a particular target throughput. Sleep transistors are traditionally used to power gate idle circuits, however, these transistors have fundamental limitations in their effectiveness. Alternatively, MEM/NEM relays with zero leakage current can achieve greater energy savings under a certain data rate and design architecture. An asynchronous FIR filter 4 phase bundled data handshake protocol is presented. Implementation is accomplished in 90nm technology node and simulation exercised at various data rates and design complexities. It was demonstrated that our proposed approach offers 69% energy improvements at a data rate 1KHz compared to 39% of the previous work. The current trends for greater heterogeneity in future Systems-on- Chip (SoC) do not only concern their functionality but also their timing and power aspects. The increasing diversity of timing and power supply conditions, and associated concurrently operating modes, within an SoC calls for more efficient power delivery networks (PDN) for battery operated devices. This is especially important for systems with mixed duty cycling, where some parts are required to work regularly with low-throughput while other parts are activated spontaneously, i.e. in bursts. To improve their reaction time vs energy efficiency, this work proposes to incorporate a power-switching network based on MEM relays to switch the SoC power-performance state (PPS) into an active mode while eliminating the leakage current when it is idle. Results show that even with today0s large and high pull-in voltages, a MEM-relay-based power switching network (PSN) can achieve a 1000x savings in energy compared to its CMOS counterpart for low duty cycle. A simple case of optimising an on-chip charge pump required to switch-on the relay has been investigated and its energy-latency overhead has been evaluated. Heterogeneous many-core systems are increasingly being employed in modern embedded platforms for high throughput at low energy cost considerations. These applications typically exhibit bursty workloads that provide opportunities to minimize system energy. CMOS-based power gating circuitry, typically consisting of sleep transistors, is used as an effective technique for idle energy reduction in such applications. However, these transistors contribute high leakage current when driving large capacitive loads, making effective energy minimization challenging. This thesis proposes a novel MEMS-based idle energy control approach. Core to this approach is an integrated sleep mode management based on the performance-energy states and bursty workloads indicated by the performance counters. A number of PARSEC benchmark applications are used as case studies of bursty workloads, including CPU- and memory- intensive ones. These applications are exercised on an Exynos 5422 heterogeneous many-core platform, engineered with a performance counter facilities, showing 55.5% energy savings compared with an on-demand governor. Furthermore, an extensive trade-off analysis demonstrates the comparative advantages of the MEMS-based controller, including zero-leakage current and non-invasive implementations suitable for commercial off-the-shelf systems.Higher committee of education development in Iraq (HCED

Interrogation of Single Asperity Electrical Contacts Using atomic force Microscopy With Application to Nems Logic Switches

Energy consumption by computers and electronics is currently 15% of worldwide energy output, and growing. Aggressive scaling of the fully-electronic transistor, which is the fundamental computational element of these devices, has led to significant and immutable energy losses. Ohmic nanoelectromechanical systems (NEMS) logic switches have been recognized as a potential transistor replacement technology with projected energy savings of one to three orders of magnitude over traditional, fully-electronic transistors. However, the use of conventional, adhesive contact materials (i.e. metals) in NEMS switches electrical contacts leads to permanent device seizure or the formation of insulating tribofilms that inhibits commercialization of this technology. Of critical need is a method to efficiently identify and interrogate low adhesion, chemically stable electrical contact material pairs under conditions and scales relevant to NEMS logic switch contacts. This thesis presents the development of two electrical contact testing methods based on atomic force microscopy (AFM) to interrogate electrical contact materials under contact forces and environments representative of NEMS logic switch operating conditions. AFM was used to mimic the interaction of Pt/Pt NEMS logic switch electrical interfaces for up to two billion contact cycles in laboratory timeframes. Contact resistance before cycling significantly exceeded theoretical predictions for clean Pt/Pt interfaces due to adsorbed contaminant films and increased up to six orders of magnitude due to cycling-induced insulating tribopolymer growth. Sliding of the contact with microscale amplitudes lead to significant recovery of conductivity through displacement of the insulating films. Based on this observation, AFM was then used to investigate the role of load, shear, electrical bias, and environment on the electrical robustness of Pt/nitrogen-incorporated ultrananocrystalline diamond (N-UNCD) and Pt/Pt interfaces. N-UNCD was selected because similar diamond films have demonstrated low adhesion, chemical inertness, and compatibility with NEMS logic device fabrication. Pt/N-UNCD interfaces subjected to low loads during sliding demonstrated significant increases in contact resistance due to insulating film formation that was not observed at larger loads. Taken in concert, these finding demonstrate the capability of AFM to investigate nanoscale electrical contact phenomena without the need for time-consuming and expensive integration of unproven materials in NEMS logic switches