Modeling Solder Ball Array Interconnects for Power Module Optimization

PowerSynth is a software platform that can co-optimize power modules utilizing a 2D topology and wire bond interconnects. The novel 3D architectures being proposed at the University of Arkansas utilize solder ball interconnects instead of wire bonds. Therefore, they currently cannot be optimized using PowerSynth. This paper examines methods to accurately model the parasitic inductance of solder balls and ball grid arrays so they may be implemented into software for optimization. Proposed mathematical models are validated against ANSYS Electromagnetics Suite simulations. A comparison of the simulated data shows that mathematical models are well suited for implementation into optimization software platforms. Experimental measurements proved to be inconclusive and necessitate future work

Enabling More than Moore: Accelerated Reliability Testing and Risk Analysis for Advanced Electronics Packaging

For five decades, the semiconductor industry has distinguished itself by the rapid pace of improvement in miniaturization of electronics products-Moore's Law. Now, scaling hits a brick wall, a paradigm shift. The industry roadmaps recognized the scaling limitation and project that packaging technologies will meet further miniaturization needs or ak.a "More than Moore". This paper presents packaging technology trends and accelerated reliability testing methods currently being practiced. Then, it presents industry status on key advanced electronic packages, factors affecting accelerated solder joint reliability of area array packages, and IPC/JEDEC/Mil specifications for characterizations of assemblies under accelerated thermal and mechanical loading. Finally, it presents an examples demonstrating how Accelerated Testing and Analysis have been effectively employed in the development of complex spacecraft thereby reducing risk. Quantitative assessments necessarily involve the mathematics of probability and statistics. In addition, accelerated tests need to be designed which consider the desired risk posture and schedule for particular project. Such assessments relieve risks without imposing additional costs. and constraints that are not value added for a particular mission. Furthermore, in the course of development of complex systems, variances and defects will inevitably present themselves and require a decision concerning their disposition, necessitating quantitative assessments. In summary, this paper presents a comprehensive view point, from technology to systems, including the benefits and impact of accelerated testing in offsetting risk

The durability of solder joints under thermo-mechanical loading; application to Sn-37Pb and Sn-3.8Ag-0.7Cu lead-free replacement alloy

Solder joints in electronic packages provide mechanical, electrical and thermal connections. Hence, their reliability is also a major concern to the electronic packaging industry. Ball Grid Arrays (BGAs) are a very common type of surface mount technology for electronic packaging. This work primarily addresses the thermo-mechanical durability of BGAs and is applied to the exemplar alloys; traditional leaded solder and a popular lead-free solder. Isothermal mechanical fatigue tests were carried out on 4-ball test specimens of the lead-free (Sn-3.8Ag-0.7Cu) and leaded (Sn-37Pb) solder under load control at room temperature, 35°C and 75°C. As well as this, a set of combined thermal and mechanical cycling tests were carried out, again under load control with the thermal cycles either at a different frequency from the mechanical cycles (not-in-phase) or at the same frequency (both in phase and out-of-phase). The microstructural evaluation of both alloys was investigated by carrying out a series of simulated ageing tests, coupled with detailed metallurgical analysis and hardness testing. The results were treated to produce stress-life, cyclic behaviour and creep curves for each of the test conditions. Careful calibration allowed the effects of substrate and grips to be accounted for and so a set of strain-life curves to be produced. These results were compared with other results from the literature taking into account the observations on microstructure made in the ageing tests. It is generally concluded that the TMF performance is better for the Sn-Ag-Cu alloy than for the Sn-Pb alloy, when expressed as stress-life curves. There is also a significant effect on temperature and phase for each of the alloys, the Sn-Ag-Cu being less susceptible to these effects. When expressed as strain life, the effects of temperature, phase and alloy type are much diminished. Many of these conclusions coincided with only parts of the literature and reasons for the remaining differences are advanced

Development of interconnections for mm-wave antenna module package

Abstract. The increase in mobile network data usage has led to interests in mm-wave frequencies (for example 26.5–29.5 GHz) on becoming fifth generation (5G) networks in addition to previously used sub-6 GHz frequencies. The advantage of mm-wave frequencies is larger bandwidth, leading to larger throughput with a tradeoff of smaller coverage due to shorter wavelength. The coverage issue can be compensated by using antenna arrays instead of one antenna. There have been some studies about stacking antenna module package vertically on motherboard, and in more advanced approach, the RFIC is integrated into the bottom of the antenna module package. This thesis concentrates on developing the interconnection between two PWBs on mm-wave frequency (26.5–29.5 GHz) between the antenna module and motherboard. More accurately, creating interconnection around via structure, carrying RF-signal from antenna module to motherboard by applying vertical stacking. This method may reduce the overall price of the system, while increasing the level of integration in the system. The overall aim of this thesis was to provide a functional and optimized interconnection method with measurement results and limitations of Nokia Factory. The interconnection can be created by using electromagnetic coupling or galvanic connection. The galvanic connection was chosen for many reasons and different interconnection methods applying galvanic connection were introduced. These methods include LGA and BGA soldering, traditional RF-connector and antenna array connector with 16-ports. After considering the options and Nokia Factory limitations, the most suitable interconnection method turned out to be LGA soldering. The research work includes partial design of antenna module and motherboard, and the optimization for connection. Prototypes were created based on the design, and the measurement results and conclusions of interconnection functionality were provided as well. Six prototypes were made, from which prototypes 3–6 were functional in terms of solder height. The measurement results show that there was variation in matching between different prototypes and between simulation and measurement results. By doing x-ray and failure analysis, a few reasons were found to explain the variation. One reason can be found from voids in signal soldering, which widens the soldering horizontally, leading to decreased matching due to changed solder diameter and asymmetric grounding. However, by utilizing the solder bumping method, the appearance and diameter of voids can be minimized. The conclusion with prototypes was that the system functions well, but improvements are recommended, and simulations should be re-done with modifications from failure analysis. Overall, the aim of the thesis was reached.Antennimoduulipaketin liitäntöjen kehittäminen millimetriaalto taajuuksille. Tiivistelmä. Datankäytön jatkuvan kasvun takia viidennen sukupolven (5G) matkapuhelinteknologian kehitys on keskittynyt aiemmin käytettyjen alle 6 GHz taajuuksien lisäksi uusille, korkeammille, millimetriaaltojen (esim. 26.5–29.5 GHz) taajuuskaistalle. Korkeammat taajuudet tarjoavat mahdollisuuden käyttää suurempia kaistanleveyksiä kasvattaen läpikulkevan datan määrää, mutta sen hintana on signaalin kantomatkan pienentyminen aallonpituuden pienentymisen takia. Kantomatkan lyhenemistä voidaan kuitenkin kompensoida käyttämällä antenniryhmiä yksittäisten antennien asemasta. Antenniryhmien integroinnista systeemiin on tehty erilaisia tutkimuksia, joita ovat esimerkiksi vertikaalinen pinoaminen, jossa antennilevy juotetaan toiselle piirilevylle. Edistyksellisemmässä versiossa kyseisen antennilevyn pohjaan on liitetty RFIC piiri. Tässä diplomityössä tutkittiin kahden piirilevyn välistä liityntäkohtaa vertikaalisella pinoamisella. Liityntäkohta kuljettaa millimetriaaltotaajuista RF-signaalia (26.5–29.5 GHz) antennilevyltä äitilevylle. Kyseisellä rakenteella voidaan saada pienennettyä mahdollisen tuotteen kustannuksia, samalla pienentäen myös sen fyysistä kokoa. Työn tarkoituksena on tarjota Nokialle valmiiksi optimoitu liitäntäratkaisu mittaustuloksineen ja tuotannon rajoitteineen dokumentoituna. Tutkittu liityntäkohta voidaan muodostaa sähkömagneettisella kytkeytymisellä tai galvaanisesti, joista jälkimmäinen on huomattavasti järkevämpi ja tässä työssä on esitetty sille erilaisia vaihtoehtoja, joita on vertailtu toisiinsa. Näihin vaihtoehtoihin sisältyy koneellinen juottaminen LGA tai BGA tavalla, RF-liittimien käyttö ja antenniryhmää varten kehitetty 16 porttinen liitin. Kyseisistä liitäntä vaihtoehdoista parhaaksi ja soveltuvimmaksi osoittautui LGA juotos. Tutkimustyö sisältää antennilevyn ja äitilevyn osittaisen suunnittelun ja optimoinnin, ja sen perusteella tehdyn prototyypin, mittaustulokset ja päätelmät liitynnän toimivuudesta. Prototyyppejä tehtiin kaikkiaan kuusi, joista viimeiset 3–6 olivat onnistuneita juotospaksuuden perusteella. Mittausten perusteella sovituksessa on paljon vaihtelua, jolle löydettiin muutamia syitä röntgen tarkastuksessa ja virheanalyysissa. Näihin syihin sisältyy juotoksesta löytyneet kaasukuplat, jotka johtavat juotoksen laajenemiseen horisontaalisesti, mikä taas heikentää maadoitusta ja täten sovitusta. Juotoksen kaasukuplat voidaan kuitenkin välttää niin kutsutulla juotoksen pallottamisella (Engl. Solder Bumping), jossa kaasukuplia ilmeni huomattavasti vähemmän ja ne olivat pienempiä. Lopputulemana todettiin, että työ on onnistunnut ja prototyyppi on toimiva, mutta tarjotut kehitysideat kannattaa huomioida mahdollisessa jatkokehityksessä ja simuloinnit tulisi tehdä uudelleen virheanalyysistä saaduilla arvoilla ja tiedoilla

Materials jetting for advanced optoelectronic interconnect: technologies and application

This report covers the work carried out on Teaching Company Scheme No. 2275 "Materials Jetting for Advanced Interconnect" between February 1998 and February 2000. The project was conducted at the Harlow laboratories of Nortel Networks with the support of the Department of Manufacturing Engineering of Loughborough University. Technical direction and supervision has been provided by Mr Paul Conway, Reader, at Loughborough University, Professor Ken Snowdon and Mr Chris Tanner of Nortel Networks. The aim of the project was to produce and deposit minute and precise volumes of a range of materials, such as metallic alloys, glasses and polymers, onto a variety of substrates commonly used in the electronics and optoelectronics fields. The technology, which is analogous to ink-jet printing, firstly had to be refined to accommodate higher processing temperatures of up to 350°C. The ultimate project deliverable was to produce a specification for jetting equipment suited towards volume manufacturing. [Continues.

Compliant copper microwire arrays for reliable interconnections between large low-CTE packages and printed wiring board

The trend to high I/O density, performance and miniaturization at low cost is driving the industry towards shrinking interposer design rules, requiring a new set of packaging technologies. Low-CTE packages from silicon, glass and low-CTE organic substrates enable high interconnection density, high reliability and integration of system components. However, the large CTE mismatch between the package and the board presents reliability challenges for the board-level interconnections. Novel stress-relief structures that can meet reliability requirements along with electrical performance while meeting the cost constraints are needed to address these challenges. This thesis focuses on a comprehensive methodology starting with modeling, design, fabrication and characterization to validate such stress-relief structures. This study specifically explores SMT-compatible stress-relief microwire arrays in thin polymer carriers as a unique and low-cost solution for reliable board-level interconnections between large low-CTE packages and printed wiring boards. The microwire arrays are pre-fabricated in ultra-thin carriers using low-cost manufacturing processes such as laser vias and copper electroplating, which are then assembled in between the interposer and printed wiring board (PWB) as stress-relief interlayers. The microwire array results in dramatic reduction in solder stresses and strains, even with larger interposer sizes (20 mm × 20 mm), at finer pitch (400 microns), without the need for underfill. The parallel wire arrays result in low resistance and inductance, and therefore do not degrade the electrical performance. The scalability of the structures and the unique processes, from micro to nanowires, provides extendibility to finer pitch and larger package sizes. Finite element method (FEM) was used to study the reliability of the interconnections to provide guidelines for the test vehicle design. The models were built in 2.5D geometries to study the reliability of 400 µm-pitch interconnections with a 100 µm thick, 20 mm × 20 mm silicon package that was SMT-assembled onto an organic printed wiring board. The performance of the microwire array interconnection is compared to that of ball grid array (BGA) interconnections, in warpage, equivalent plastic strain and projected fatigue life. A unique set of materials and processes was used to demonstrate the low-cost fabrication of microwire arrays. Copper microwires with 12 µm diameter and 50 µm height were fabricated on both sides of a 50 µm thick, thermoplastic polymer carrier using dryfilm based photolithography and bottom-up electrolytic plating. The copper microwire interconnections were assembled between silicon interposer and FR-4 PWB through SMT-compatible process. Thermal mechanical reliability of the interconnections was characterized by thermal cycling test from -40°C to 125°C. The initial fatigue failure in the interconnections was identified at 700 cycles in the solder on the silicon package side, which is consistent with the modeling results. This study therefore demonstrated a highly-reliable and SMT-compatible solution for board-level interconnections between large low-CTE packages and printed wiring board.Ph.D

Thermal Cycling Life Prediction of Sn-3.0Ag-0.5Cu Solder Joint Using Type-I Censored Data

Because solder joint interconnections are the weaknesses of microelectronic packaging, their reliability has great influence on the reliability of the entire packaging structure. Based on an accelerated life test the reliability assessment and life prediction of lead-free solder joints using Weibull distribution are investigated. The type-I interval censored lifetime data were collected from a thermal cycling test, which was implemented on microelectronic packaging with lead-free ball grid array (BGA) and fine-pitch ball grid array (FBGA) interconnection structures. The number of cycles to failure of lead-free solder joints is predicted by using a modified Engelmaier fatigue life model and a type-I censored data processing method. Then, the Pan model is employed to calculate the acceleration factor of this test. A comparison of life predictions between the proposed method and the ones calculated directly by Matlab and Minitab is conducted to demonstrate the practicability and effectiveness of the proposed method. At last, failure analysis and microstructure evolution of lead-free solders are carried out to provide useful guidance for the regular maintenance, replacement of substructure, and subsequent processing of electronic products

Fundamental Studies of Tin Whiskering in Microelectronics Finishes

Fundamental Studies of Tin Whiskering in Microelectronics Finishes Abstract Common electronics materials, such as tin, copper, steel, and brass, are ambient reactive under common use conditions, and as such are prone to corrosion. During the early 1940s, reports of failures due to electrical shorting of components caused by `whisker' (i.e., filamentary surface protrusion) growth on many surface types - including the aforementioned metals - began to emerge. Lead alloying of tin (3-10% by weight, typically in the eutectic proportion) eliminated whiskering risk for decades, until the July 2006 adoption of the Restriction of Hazardous Substances (RoHS) directive was issued by the European Union. This directive, which has since been adopted by California and parts of China, severely restricted the use of lead (<1000 ppm) in all electrical and electronics equipment being placed on the EU market, imposing the need for developing reliable new "lead-free" alternatives to SnPb. In spite of the abundance of modern-day anecdotes chronicling whisker-related failures in satellites, nuclear power stations, missiles, pacemakers, and spacecraft navigation equipment, pure tin finishes are still increasingly being employed today, and the root cause(s) of tin whiskering remains elusive. This work describes a series of structured experiments exploring the fundamental relationships between the incidence of tin whiskering (as dependent variable) and numerous independent variables. These variables included deposition method (electroplating, electroless plating, template-based electrochemical synthesis, and various physical vapor deposition techniques, including resistive evaporation, electron beam evaporation, and sputtering), the inclusion of microparticles and organic contamination, the effects of sample geometry, and nanostructuring. Key findings pertain to correlations between sample geometry and whisker propensity, and also to the stress evolution across a series of 4"-diameter silicon wafers of varying thicknesses with respect to the degree of post-metallization whiskering. Regarding sample geometry, it was found that smaller, thinner substrates displayed a more rapid onset of whiskering immediately following metallization. Changes in wafer-level stress were not found to correlate with whiskering morphology (number, density, length) after 6 weeks of aging. This result points either to the irrelevance of macrostress in the substrate/film composite, or to a difference in whiskering mechanism for rigid substrates (whose stress gradient over time is significant) when compared with thinner, flexible susbtrates (whose stress is less variable with time). Organic contamination was found to have no appreciable effect when explicitly introduced. Furthermore, electron-beam evaporated films whiskered more readily than films deposited via electroplating from baths containing organic "brighteners." Beyond such findings, novel in themselves, our work is also unique in that we emphasize the "clean" deposition of tin (with chromium adhesion layers and copper underlayers) by vacuum-based physical vapor deposition, to circumvent the question of contamination entirely. By employing silicon substrates exclusively, we have distinguished ourselves from other works (which, for example, use copper coupons fabricated from rolled shim stock) because we have better sample-to-sample consistency in terms of material properties, machinability, and orientation