A Holistic Methodology for System Margining and Jitter Tolerance Optimization in Post-Silicon Validation

The optimization of receiver analog circuitry in modern high-speed input/output (HSIO) links is a very time consuming post-silicon validation process. Current industrial practices are based on exhaustive enumeration methods to improve either the system margins or the jitter tolerance compliance test. In this paper, these two requirements are addressed in a holistic optimization-based approach. We propose an innovative objective function based on these two metrics. Our method employs Kriging to build a surrogate model based on system margining and jitter tolerance measurements. The proposed method is able to deliver optimal system margins and guarantee jitter tolerance compliance while substantially decreasing the typical post-Si validation time

A Holistic Formulation for System Margining and Jitter Tolerance Optimization in Industrial Post-Silicon Validation

There is an increasingly higher number of mixed-signal circuits within microprocessors and systems on chip (SoC). A significant portion of them corresponds to high-speed input/output (HSIO) links. Post-silicon validation of HSIO links can be critical for making a product release qualification decision under aggressive launch schedules. The optimization of receiver analog circuitry in modern HSIO links is a very time consuming post-silicon validation process. Current industrial practices are based on exhaustive enumeration methods to improve either the system margins or the jitter tolerance compliance test. In this paper, these two requirements are addressed in a holistic optimization-based approach. We propose a novel objective function based on these two metrics. Our method employs Kriging to build a surrogate model based on system margining and jitter tolerance measurements. The proposed method, tested with three different realistic server HSIO links, is able to deliver optimal system margins and guarantee jitter tolerance compliance while substantially decreasing the typical post-silicon validation time.ITESO, A.C

Efficient Characterization of Transmitter Output Jitter Components in 100GBASE-CR4 Ethernet

Electrical data communication links less than 10 meters long are increasing link rates at a steady pace. As link rate increases, timing tolerances become more important to ensure low bit error rates (BER). Ensuring high performance links in scenarios with large amounts of crosstalk requires the characterization of transmitter output jitter (TOJ). Some jitter models are incapable of effectively separating Gaussian random jitter from jitter caused by crosstalk. To overcome this, IEEE 802.3-2018 Clause 92 100GBASE-CR4 defines TOJ tests using the dual-Dirac (��-��) model. Additionally the 100GBASE-CR4 TOJ test definition separates out components of jitter by selecting isolated edges in a test pattern to be sampled. Applying the ��-�� model to specific edges in a test pattern is not widely present in other jitter test methodologies. In this thesis the IEEE 802.3-2018 Clause 92 TOJ tests are implemented, and issues related to measurement time, captured data size, and measurement accuracy are addressed. A set of measurements were taken of a signal generator with a set of expected worst case jitter components applied to the signal. These measurements are explored to validate the implementation and examine limitations of the test definition

The digital data processing concepts of the LOFT mission

The Large Observatory for X-ray Timing (LOFT) is one of the five mission candidates that were considered by ESA for an M3 mission (with a launch opportunity in 2022 - 2024). LOFT features two instruments: the Large Area Detector (LAD) and the Wide Field Monitor (WFM). The LAD is a 10 m 2 -class instrument with approximately 15 times the collecting area of the largest timing mission so far (RXTE) for the first time combined with CCD-class spectral resolution. The WFM will continuously monitor the sky and recognise changes in source states, detect transient and bursting phenomena and will allow the mission to respond to this. Observing the brightest X-ray sources with the effective area of the LAD leads to enormous data rates that need to be processed on several levels, filtered and compressed in real-time already on board. The WFM data processing on the other hand puts rather low constraints on the data rate but requires algorithms to find the photon interaction location on the detector and then to deconvolve the detector image in order to obtain the sky coordinates of observed transient sources. In the following, we want to give an overview of the data handling concepts that were developed during the study phase.Comment: Proc. SPIE 9144, Space Telescopes and Instrumentation 2014: Ultraviolet to Gamma Ray, 91446

Safety-Critical Communication in Avionics

The aircraft of today use electrical fly-by-wire systems for manoeuvring. These safety-critical distributed systems are called flight control systems and put high requirements on the communication networks that interconnect the parts of the systems. Reliability, predictability, flexibility, low weight and cost are important factors that all need to be taken in to consideration when designing a safety-critical communication system. In this thesis certification issues, requirements in avionics, fault management, protocols and topologies for safety-critical communication systems in avionics are discussed and investigated. The protocols that are investigated in this thesis are: TTP/C, FlexRay and AFDX, as a reference protocol MIL-STD-1553 is used. As reference architecture analogue point-to-point is used. The protocols are described and evaluated regarding features such as services, maturity, supported physical layers and topologies.Pros and cons with each protocol are then illustrated by a theoretical implementation of a flight control system that uses each protocol for the highly critical communication between sensors, actuators and flight computers.The results show that from a theoretical point of view TTP/C could be used as a replacement for a point-to-point flight control system. However, there are a number of issues regarding the physical layer that needs to be examined. Finally a TTP/C cluster has been implemented and basic functionality tests have been conducted. The plan was to perform tests on delays, start-up time and reintegration time but the time to acquire the proper hardware for these tests exceeded the time for the thesis work. More advanced testing will be continued here at Saab beyond the time frame of this thesis

Analysis of jitter influence in fast frequency measurements

This paper presents a theoretical analysis of possible jitter impact in application of numeric criterion for fastmeasurement of frequency by coincidence principle. The primary goal is the generation of a signal containing a known amount of each jitter components. This signal was used for testing signals with regular pulse trains. Initially, jitter components are analyzed and modeled individually. Next, sequences for combining different kinds of jitter are modeled, simulated and evaluated. Jitter model simulation in Matlab is utilized to show the independence of frequencymeasurement results on the total jitter present in the reference and desired pulse trains independently. A good agreement between previously introduced theory of fastmeasurement of frequency and simulation in jitter presence is verified; these results allows to engineers use the numeric criterion for fastmeasurement of frequency in spite to interactions among jitter components in various applications for frequency domain sensors

Unified Synchronized Data Acquisition Networks

The permanently evolving technical area of communication technology and the presence of more and more precise sensors and detectors, enable options and solutions to challenges in science and industry. In high-energy physics, for example, it becomes possible with accurate measurements to observe particles almost at the speed of light in small-sized dimensions. Thereby, the enormous amounts of gathered data require modern high performance communication networks. Potential and efficient implementation of future readout chains will depend on new concepts and mechanisms. The main goals of this dissertation are to create new efficient synchronization mechanisms and to evolve readout systems for optimization of future sensor and detector systems. This happens in the context of the Compressed Baryonic Matter experiment, which is a part of the Facility for Antiproton and Ion Research, an international accelerator facility. It extends an accelerator complex in Darmstadt at the GSI Helmholtzzentrum für Schwerionenforschung GmbH. Initially, the challenges are specified and an analysis of the state of the art is presented. The resulting constraints and requirements influenced the design and development described within this dissertation. Subsequently, the different design and implementation tasks are discussed. Starting with the basic detector read system requirements and the definition of an efficient communication protocol. This protocol delivers all features needed for building of compact and efficient readout systems. Therefore, it is advantageous to use a single unified connection for processing all communication traffic. This means not only data, control, and synchronization messages, but also clock distribution is handled. Furthermore, all links in this system have a deterministic latency. The deterministic behavior enables establishing a synchronous network. Emerging problems were solved and the concept was successfully implemented and tested during several test beam times. In addition, the implementation and integration of this communication methodology into different network devices is described. Therefore, a generic modular approach was created. This enhances ASIC development by supporting them with proven hardware IPs, reducing design time, and risk of failure. Furthermore, this approach delivers flexibility concerning data rate and structure for the network system. Additionally, the design and prototyping for a data aggregation and concentrator ASIC is described. In conjunction with a dense electrical to optical conversion, this ASIC enables communication with flexible readout structures for the experiment and delivers the planned capacities and bandwidth. In the last part of the work, analysis and transfer of the created innovative synchronization mechanism into the area of high performance computing is discussed. Finally, a conclusion of all reached results and an outlook of possible future activities and research tasks within the Compressed Baryonic Matter experiment are presented

Development of new readout electronics for the ATLAS LAr calorimeter at the sLHC

The ATLAS Liquid Argon (LAr) calorimeter consists of 182,486 detector cells whose signals need to be read out, digitized and processed, in order to provide signal timing and the energy deposited in each detector element. The current readout electronics is not designed to sustain the ten times higher radiation levels expected at sLHC in the years beyond 2017, and will be replaced by new electronics with a completely different readout scheme. The future on-detector electronics is planned to send out all data continuously at each bunch crossing, as opposed to the current system which only transfers data at a trigger-accept signal. Multiple high-speed and radiation-resistant optical links will transmit 100 Gbps per front-end board, each covering 128 readout channels. The off-detector processing units will not only process the data in real-time and provide digital data buffering, but will also implement trigger algorithms. An overview about the various components necessary to develop such a complex system will be given. The current R&D activities and architectural studies of the LAr Calorimeter group will be presented, in particular the on-going design of the mixed-signal and radiation hard front-end ASICs, the Silicon-on-Saphire (SOS) based optical-link, the high-speed off-detector FPGA based processing units and the power supply distribution scheme