32 research outputs found
Programming Quantum Computers Using Design Automation
Recent developments in quantum hardware indicate that systems featuring more
than 50 physical qubits are within reach. At this scale, classical simulation
will no longer be feasible and there is a possibility that such quantum devices
may outperform even classical supercomputers at certain tasks. With the rapid
growth of qubit numbers and coherence times comes the increasingly difficult
challenge of quantum program compilation. This entails the translation of a
high-level description of a quantum algorithm to hardware-specific low-level
operations which can be carried out by the quantum device. Some parts of the
calculation may still be performed manually due to the lack of efficient
methods. This, in turn, may lead to a design gap, which will prevent the
programming of a quantum computer. In this paper, we discuss the challenges in
fully-automatic quantum compilation. We motivate directions for future research
to tackle these challenges. Yet, with the algorithms and approaches that exist
today, we demonstrate how to automatically perform the quantum programming flow
from algorithm to a physical quantum computer for a simple algorithmic
benchmark, namely the hidden shift problem. We present and use two tool flows
which invoke RevKit. One which is based on ProjectQ and which targets the IBM
Quantum Experience or a local simulator, and one which is based on Microsoft's
quantum programming language Q.Comment: 10 pages, 10 figures. To appear in: Proceedings of Design, Automation
and Test in Europe (DATE 2018
Synthesis of Linear Reversible Circuits and EXOR-AND-based Circuits for Incompletely Specified Multi-Output Functions
At this time the synthesis of reversible circuits for quantum computing is an active area of research. In the most restrictive quantum computing models there are no ancilla lines and the quantum cost, or latency, of performing a reversible form of the AND gate, or Toffoli gate, increases exponentially with the number of input variables. In contrast, the quantum cost of performing any combination of reversible EXOR gates, or CNOT gates, on n input variables requires at most O(n2/log2n) gates. It was under these conditions that EXOR-AND-EXOR, or EPOE, synthesis was developed.
In this work, the GF(2) logic theory used in EPOE is expanded and the concept of an EXOR-AND product transform is introduced. Because of the generality of this logic theory, it is adapted to EXOR-AND-OR, or SPOE, synthesis. Three heuristic spectral logic synthesis algorithms are introduced, implemented in a program called XAX, and compared with previous work in classical logic circuits of up to 26 inputs. Three linear reversible circuit methods are also introduced and compared with previous work in linear reversible logic circuits of up to 100 inputs
Synthesis and testing of reversible Toffoli circuits
xii, 82 leaves : ill. ; 29 cmRecently, researchers have been interested in reversible computing because of its ability to
dissipate nearly zero heat and because of its applications in quantum computing and low
power VLSI design. Synthesis and testing are two important areas of reversible logic. The
thesis first presents an approach for the synthesis of reversible circuits from the exclusive-
OR sum-of-products (ESOP) representation of functions, which makes better use of shared
functionality among multiple outputs, resulting in up to 75% minimization of quantum cost
compared to the previous approach. This thesis also investigates the previous work on constructing
the online testable circuits and points out some design issues. A simple approach
for online fault detection is proposed for a particular type of ESOP-based reversible circuit,
which is also extended for any type of Toffoli circuits. The proposed online testable designs
not only address the problems of the previous designs but also achieve significant improvements
of up to 78% and 99% in terms of quantum cost and garbage outputs, respectively
Templates for positive and negative control Toffoli networks
Circuit realizations obtained from existing logic synthesis approaches may not be optimal and thus one commonly applies post-synthesis optimization techniques to get better realization of the circuits. This thesis proposes two new templates (templates 4 and 7) for positive and negative control Toffoli gates as well as proposing algorithms for post synthesis optimization of reversible positive and negative control Toffoli networks by utilizing the set of templates. When applying the templates to circuits generated by the improved shared cube synthesis approach [23] a reduction in quantum cost was achieved for 86 of the 110 circuits. On average a 21.34% reduction in quantum cost was achieved, and in some cases up to 53.58% reduction was obtained.Natural Sciences and Engineering Research Council of Canada (NSERC
A Best-Fit Mapping Algorithm to Facilitate ESOP-Decomposition in Clifford+T Quantum Network Synthesis
Currently, there is a large research interest and a significant economical effort to build the first practical quantum computer. Such quantum computers promise to exceed the capabilities of conventional computers in fields such as computational chemistry, machine learning and cryptanalysis. Automated methods to map logic designs to quantum networks are crucial to fully realizing this dream, however, existing methods can be expensive both in computational time as well as in the size of the resultant quantum networks. This work introduces an efficient method to map reversible single-target gates into a universal set of quantum gates (Clifford+T). This mapping method is called best-fit mapping and aims at reducing the cost of the resulting quantum network. It exploits k-LUT mapping and the existence of clean ancilla qubits to decompose a large single-target gate into a set of smaller single-target gates. In addition this work proposes a post-synthesis optimization method to reduce the cost of the final quantum network, based on two cost-minimization properties. Results show a cost reduction for the synthesized EPFL benchmark up to 53% in the number T gates