Single-Chip Isolated DC-DC Converter with Self-Tuned Maximum Power Transfer Frequency

abstract: There is an increasing demand for fully integrated point-of-load (POL) isolated DC-DC converters that can provide an isolation barrier between the primary and the secondary side, while delivering a low ripple, low noise regulated voltage at their isolated sides to a high dynamic range, sensitive mixed signal devices, such as sensors, current-shunt-monitors and ADCs. For these applications, smaller system size and integration level is important because the whole system may need to fit to limited space. Traditional methods for providing isolated power are discrete solutions using bulky transformers. Miniaturization of isolated POL regulators is becoming highly desirable for low power applications. A fully integrated, low noise isolated point-of-load DC-DC converter for supply regulation of high dynamic range analog and mixed signal sensor signal-chains is presented. The isolated DC-DC converter utilizes an integrated planar air-core micro-transformer as a coupled resonator and isolation barrier and enables direct connection of low-voltage mixed signal circuits to higher supply rails. The air core transformer is driven at its primary resonant frequency of 100 MHz to achieve maximum power transfer. A mixed-signal perturb-and-observe based frequency search algorithm is developed to improve maximum power transfer efficiency by 60% across the isolation barrier compared to fixed driving frequency method. The isolated converter’s output ripple is reduced by utilizing spread spectrum clocking in the driver. An isolated PMOS LDO in the secondary side is used to suppress switching noise and ripple by 21dB. Conducted and radiated EMI distribution on the IC is measured by a set of integrated ring oscillator based noise sensors with -68dBm noise sensitivity. The proposed isolated converter achieves highest level of integration with respect to earlier reported integrated isolated converters, while providing 50V on-chip junction isolation without the need for extra silicon post-processing steps.Dissertation/ThesisDoctoral Dissertation Electrical Engineering 201

Adaptive Spread Spectrum Clock Generator using Delta-Sigma Digital-to-Time Converter

修士論

On low frequency conducted EMI: interference mitigation with focus on the DC switching harmonic in the time and frequency domains

The recent increase of interconnected electrical systems such as power supplies and communication links are creating problems associated with electromagnetic fields generated at different voltage levels and frequencies. Semiconductor switches used in for example Switched Mode Power Supplies are constantly increasing in power rating and frequency limits. In addition, wired communication links are also increasing the working bandwidth and channel capability to transfer more information in less time. Smart grids are receiving much attention from companies and researchers all over the world. Two concerns that drive the research carried out on smart grids are Power Quality and Signal Integrity. This work presents an analysis of conducted emissions with two aims. Firstly, an analysis is made of the simulated and measured data when a DC system generates electromagnetic interference and how to improve or mitigate it with certain frequency modulation techniques by spreading the spectrum of the switching frequency in agreement to an established standard. Secondly, a demonstration of the coupling effects as one of the major concerns when dealing with Electromagnetic Interference sources is presented experimentally. Statistical analyses for these tests are performed to understand the main causes and possible actions to suppress interference and to address Electromagnetic Compatibility between devices. The work presents the following findings. An understanding of the important parameters for frequency modulation techniques called as Spread Spectrum. These parameters are the rate of change for the modulating signal and the modulation index that controls the switching frequency of a modulated DC-DC converter to mitigate the interference measured. The importance of an auxiliary time domain (Bit Error Rate) analysis to measure the interference of a DC-DC converter modulated by Spread Spectrum to understand the main drawback in the emissions measured from a different point of view by means of a Crosstalk environment. The conclusion that Bit Error Rate measurement of a communication signal cannot be decreased using Spread Spectrum Modulation for the power converter as the EMI source. The results obtained use data measured using an EMI receiver and where possible a simulation describing the most important parameters. This work provides interesting and useful points to analyse the Spread Spectrum technique applied to DC power converters and the main advantages and disadvantages

On low frequency conducted EMI: interference mitigation with focus on the DC switching harmonic in the time and frequency domains

The recent increase of interconnected electrical systems such as power supplies and communication links are creating problems associated with electromagnetic fields generated at different voltage levels and frequencies. Semiconductor switches used in for example Switched Mode Power Supplies are constantly increasing in power rating and frequency limits. In addition, wired communication links are also increasing the working bandwidth and channel capability to transfer more information in less time. Smart grids are receiving much attention from companies and researchers all over the world. Two concerns that drive the research carried out on smart grids are Power Quality and Signal Integrity. This work presents an analysis of conducted emissions with two aims. Firstly, an analysis is made of the simulated and measured data when a DC system generates electromagnetic interference and how to improve or mitigate it with certain frequency modulation techniques by spreading the spectrum of the switching frequency in agreement to an established standard. Secondly, a demonstration of the coupling effects as one of the major concerns when dealing with Electromagnetic Interference sources is presented experimentally. Statistical analyses for these tests are performed to understand the main causes and possible actions to suppress interference and to address Electromagnetic Compatibility between devices. The work presents the following findings. An understanding of the important parameters for frequency modulation techniques called as Spread Spectrum. These parameters are the rate of change for the modulating signal and the modulation index that controls the switching frequency of a modulated DC-DC converter to mitigate the interference measured. The importance of an auxiliary time domain (Bit Error Rate) analysis to measure the interference of a DC-DC converter modulated by Spread Spectrum to understand the main drawback in the emissions measured from a different point of view by means of a Crosstalk environment. The conclusion that Bit Error Rate measurement of a communication signal cannot be decreased using Spread Spectrum Modulation for the power converter as the EMI source. The results obtained use data measured using an EMI receiver and where possible a simulation describing the most important parameters. This work provides interesting and useful points to analyse the Spread Spectrum technique applied to DC power converters and the main advantages and disadvantages

A Unified Design Theory for Class-E Resonant DC–DC Converter Topologies

Resonant and quasi-resonant dc-dc converters have been introduced to increase the operating frequency of switching power converters, with advantages in terms of performance, cost, and/or size. In this paper, we focus on class-E resonant topologies, and we show that about twenty different architectures proposed in the last three decades can be reduced to two basic topologies, allowing the extension to all these resonant converters of an exact and straightforward design procedure that has been recently proposed. This represents an important breakthrough with respect to the state of the art, where class-E circuit analysis is always based on strong simplifying assumptions, and the final circuit design is achieved by means of numerical simulations. The potentialities of the proposed exact methodology are highlighted by realistic circuit-level simulations, where the desired waveforms are obtained in one single step without the need of a time-consuming iterative trial-and-error process

Architectures and Circuits Leveraging Injection-Locked Oscillators for Ultra-Low Voltage Clock Synthesis and Reference-less Receivers for Dense Chip-to-Chip Communications

High performance computing is critical for the needs of scientific discovery and economic competitiveness. An extreme-scale computing system at 1000x the performance of today’s petaflop machines will exhibit massive parallelism on multiple vertical fronts, from thousands of computational units on a single processor to thousands of processors in a single data center. To facilitate such a massively-parallel extreme-scale computing, a key challenge is power. The challenge is not power associated with base computation but rather the problem of transporting data from one chip to another at high enough rates. This thesis presents architectures and techniques to achieve low power and area footprint while achieving high data rates in a dense very-short reach (VSR) chip-to-chip (C2C) communication network. High-speed serial communication operating at ultra-low supplies improves the energy-efficiency and lowers the power envelop of a system doing an exaflop of loops. One focus area of this thesis is clock synthesis for such energy-efficient interconnect applications operating at high speeds and ultra-low supplies. A sub-integer clockfrequency synthesizer is presented that incorporates a multi-phase injection-locked ring-oscillator-based prescaler for operation at an ultra-low supply voltage of 0.5V, phase-switching based programmable division for sub-integer clock-frequency synthesis, and automatic calibration to ensure injection lock. A record speed of 9GHz has been demonstrated at 0.5V in 45nm SOI CMOS. It consumes 3.5mW of power at 9.12GHz and 0.052 of area, while showing an output phase noise of -100dBc/Hz at 1MHz offset and RMS jitter of 325fs; it achieves a net of -186.5 in a 45-nm SOI CMOS process. This thesis also describes a receiver with a reference-less clocking architecture for high-density VSR-C2C links. This architecture simplifies clock-tree planning in dense extreme-scaling computing environments and has high-bandwidth CDR to enable SSC for suppressing EMI and to mitigate TX jitter requirements. It features clock-less DFE and a high-bandwidth CDR based on master-slave ILOs for phase generation/rotation. The RX is implemented in 14nm CMOS and characterized at 19Gb/s. It is 1.5x faster that previous reference-less embedded-oscillator based designs with greater than 100MHz jitter tolerance bandwidth and recovers error-free data over VSR-C2C channels. It achieves a power-efficiency of 2.9pJ/b while recovering error-free data (BER 200MHz and the INL of the ILO-based phase-rotator (32- Steps/UI) is <1-LSB. Lastly, this thesis develops a time-domain delay-based modeling of injection locking to describe injection-locking phenomena in nonharmonic oscillators. The model is used to predict the locking bandwidth, and the locking dynamics of the locked oscillator. The model predictions are verified against simulations and measurements of a four-stage differential ring oscillator. The model is further used to predict the injection-locking behavior of a single-ended CMOS inverter based ring oscillator, the lock range of a multi-phase injection-locked ring-oscillator-based prescaler, as well as the dynamics of tracking injection phase perturbations in injection-locked masterslave oscillators; demonstrating its versatility in application to any nonharmonic oscillator