Correlation between pattern density and linewidth variation in silicon photonics waveguides

We describe the correlation between the measured width of silicon waveguides fabricated with 193 nm lithography and the local pattern density of the mask layout. In the fabrication process, pattern density can affect the composition of the plasma in a dry etching process or the abrasion rate in a planarization step. Using an optical test circuit to extract waveguide width and thickness, we sampled 5841 sites over a fabricated wafer. Using this detailed sampling, we could establish the correlation between the linewidth and average pattern density around the test circuit, as a function of the radius of influence. We find that the intra-die systematic width variation correlates most with the pattern density within a radius of 200 gm, with a correlation coefficient of 0.57. No correlation between pattern density and the intra-die systematic thickness variation is observed. These findings can be used to predict photonic circuit yield or to optimize the circuit layout to minimize the effect of local pattern density. (C) 2020 Optical Society of America under the terms of the OSA Open Access Publishing Agreemen

Characterization and modeling of polysilicon MEMS chemical-mechanical polishing

Thesis (M. Eng.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2004.Includes bibliographical references (p. 74-75).Heavily used in the manufacture of integrated circuits, chemical-mechanical polishing (CMP) is becoming an enabling technology for microelectromechanical systems (MEMS). To reliably use CMP in the manufacturing process, designers must be able to accurately predict the CMP process and control final surface uniformity. This thesis extends integrated circuit CMP knowledge towards MEMS applications. Experiments were performed to characterize polysilicon MEMS CMP. A new test mask was created which contains test structures relevant to MEMS. Both single and dual material polish experiments were carried out and the resulting data fit against an adapted step height density model. Results show that integrated circuit CMP models are applicable to MEMS CMP, but the models need to be adjusted in order to contend with issues inherent to MEMS CMP. Further study may be necessary to accurately and completely characterize polysilicon MEMS CMP and make improvements to the models.by Brian D. Tang.M.Eng

トランジスタ・アレイ方式に基づくアナログレイアウトにおける密度最適化

In integrated circuit design of advanced technology nodes, layout density uniformity significantly influences the manufacturability due to the CMP variability. In analog design, especially, designers are suffering from passing the density checking since there are few useful tools. To tackle this issue, we focus on a transistor-array(TA)-style analog layout, and propose a density optimization algorithm consistent with complicated design rules. Based on TA-style, we introduce a density-aware layout format to explicitly control the layout pattern density, and provide the mathematical optimization approach. Hence, a design flow incorporating our density optimization can drastically reduce the design time with fewer iterations. In a design case of an OPAMP layout in a 65nm CMOS process, the result demonstrates that the proposed approach achieves more than 48× speed-up compared with conventional manual layout, meanwhile, it shows a good circuit performance in the post-layout simulation.北九州市立大

Modeling of chemical mechanical polishing for shallow trench isolation

Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2002.Includes bibliographical references (p. 195-201).This thesis presents the nonlinear analysis, design, fabrication, and testing of an axial-gap magnetic induction micro machine, which is a two-phase planar motor in which the rotor is suspended above the stator via mechanical springs, or tethers. The micro motor is fabricated from thick layers of electroplated NiFe and copper, by our collaborators at Georgia Institute of Technology. The rotor and the stator cores are 4 mm in diameter each, and the entire motor is about 2 mm thick. During fabrication, SU-8 epoxy is used as a structural mold material for the electroplated cores. The tethers are designed to be compliant in the azimuthal direction, while preventing axial deflections and maintaining a constant air gap. This enables accurate measurements of deflections within the rotor plane via a computer microvision system. The small scale of the magnetic induction micro machine, in conjunction with the good thermal contact between its electroplated stator layers, ensures an isothermal device which can be cooled very effectively. Current densities over 109 A/m2 simultaneously through each phase is repeatedly achieved during experiments; this density is over two orders of magnitude larger than what can be achieved in conventional macro-scale machines.(cont.) More than 5 Nm of torque is obtained for an air gap of about 5 zm, making this micro motor the highest torque density micro-scale magnetic machine to date. About 0.3 buNm for the large air gap of 70 m is also achieved in systematic tests that reveal the influence of strong eddy-currents and associated nonlinear saturation within the micro motor Eddy-current effects are modeled using a finite-difference vector potential formulation. Its results demonstrate the presence of flux crowding on the stator surface, which leads to heavy saturation. To capture saturation effects, a fully nonlinear finite-difference time-domain simulation is developed to solve Maxwell's Equations within the computational space of the micro machine. To mitigate the inherent stiffness in the partial differential equations, the speed of light is artificially reduced by five orders of magnitude, taking special care that assumptions of magnetoquasistatic behavior are still met. The results from this model are in very good agreement with experimental data from the tethered magnetic induction micro motor.by Brian Lee.Ph.D

Advanced CMP processes for special substrates and for device manufacturing in MEMS applications

The present work reports on studies and process developments to utilize the chemical mechanical planarization (CMP) technology in the field of micro electrical mechanical systems (MEMS). Approaches have been undertaken to enable the manufacturing of thick film SOI (silicon-on-insulator) substrates with a high degree of flatness as well as utilizing CMP for the formation of several novel MEMS devices. Thick film SOI wafers are of high interest in MEMS manufacturing as they offer obvious benefits as a starting material or foundation for more complex structures. Precise control of the SOI layer thickness as well as the removal uniformity is of critical importance to fully utilize the benefits of this technology. By combining fixed abrasive (FA) pads for polishing and novel grinding techniques it is shown that major improvements can be achieved over the standard manufacturing sequence. Analysis of the material removal rate (MRR) dependency on several process parameters is made. Together with the FA pad vendor a suitable consumable set for SOI is generated, which shows long term stability in the generated process. A comparison with standard methods is undertaken to prove the surface and crystalline quality of the resulting substrate material is equivalent. Analysis is done to understand the microscopic mechanism of removal. The CMP process is applied to several MEMS structures to smooth deposited oxide films and to enable direct wafer bonding (DWB) at low temperatures. This allows the design of bonded multiple stack layers including heat sensitive materials such as metals. FA CMP is applied to large pattern MEMS for total planarization but also for smoothing of the surface of single protruding structures while minimizing edge rounding and preserving the original intended pattern shape. With dedicated CMP steps thick film polysilicon smoothing is demonstrated enabling DWB. The chemo-mechanical particularities of the FA pad are investigated in detail.reviewe

Conference of Microelectronic Research 1997

https://scholarworks.rit.edu/meec_archive/1006/thumbnail.jp

DFM Techniques for the Detection and Mitigation of Hotspots in Nanometer Technology

With the continuous scaling down of dimensions in advanced technology nodes, process variations are getting worse for each new node. Process variations have a large influence on the quality and yield of the designed and manufactured circuits. There is a growing need for fast and efficient techniques to characterize and mitigate the effects of different sources of process variations on the design's performance and yield. In this thesis we have studied the various sources of systematic process variations and their effects on the circuit, and the various methodologies to combat systematic process variation in the design space. We developed abstract and accurate process variability models, that would model systematic intra-die variations. The models convert the variation in process into variation in electrical parameters of devices and hence variation in circuit performance (timing and leakage) without the need for circuit simulation. And as the analysis and mitigation techniques are studied in different levels of the design ow, we proposed a flow for combating the systematic process variation in nano-meter CMOS technology. By calculating the effects of variability on the electrical performance of circuits we can gauge the importance of the accurate analysis and model-driven corrections. We presented an automated framework that allows the integration of circuit analysis with process variability modeling to optimize the computer intense process simulation steps and optimize the usage of variation mitigation techniques. And we used the results obtained from using this framework to develop a relation between layout regularity and resilience of the devices to process variation. We used these findings to develop a novel technique for fast detection of critical failures (hotspots) resulting from process variation. We showed that our approach is superior to other published techniques in both accuracy and predictability. Finally, we presented an automated method for fixing the lithography hotspots. Our method showed success rate of 99% in fixing hotspots