CMOS Integrated Power Amplifiers for RF Reconfigurable and Digital Transmitters

abstract: This dissertation focuses on three different efficiency enhancement methods that are applicable to handset applications. These proposed designs are based on three critical requirements for handset application: 1) Small form factor, 2) CMOS compatibility and 3) high power handling. The three presented methodologies are listed below: 1) A transformer-based power combiner architecture for out-phasing transmitters 2) A current steering DAC-based average power tracking circuit for on-chip power amplifiers (PA) 3) A CMOS-based driver stage for GaN-based switched-mode power amplifiers applicable to fully digital transmitters This thesis highlights the trends in wireless handsets, the motivates the need for fully-integrated CMOS power amplifier solutions and presents the three novel techniques for reconfigurable and digital CMOS-based PAs. Chapter 3, presents the transformer-based power combiner for out-phasing transmitters. The simulation results reveal that this technique is able to shrink the power combiner area, which is one of the largest parts of the transmitter, by about 50% and as a result, enhances the output power density by 3dB. The average power tracking technique (APT) integrated with an on-chip CMOS-based power amplifier is explained in Chapter 4. This system is able to achieve up to 32dBm saturated output power with a linear power gain of 20dB in a 45nm CMOS SOI process. The maximum efficiency improvement is about ∆η=15% compared to the same PA without APT. Measurement results show that the proposed method is able to amplify an enhanced-EDGE modulated input signal with a data rate of 70.83kb/sec and generate more than 27dBm of average output power with EVM<5%. Although small form factor, high battery lifetime, and high volume integration motivate the need for fully digital CMOS transmitters, the output power generated by this type of transmitter is not high enough to satisfy the communication standards. As a result, compound materials such as GaN or GaAs are usually being used in handset applications to increase the output power. Chapter 5 focuses on the analysis and design of two CMOS based driver architectures (cascode and house of cards) for driving a GaN power amplifier. The presented results show that the drivers are able to generate ∆Vout=5V, which is required by the compound transistor, and operate up to 2GHz. Since the CMOS driver is expected to drive an off-chip capacitive load, the interface components, such as bond wires, and decoupling and pad capacitors, play a critical role in the output transient response. Therefore, extensive analysis and simulation results have been done on the interface circuits to investigate their effects on RF transmitter performance. The presented results show that the maximum operating frequency when the driver is connected to a 4pF capacitive load is about 2GHz, which is perfectly matched with the reported values in prior literature.Dissertation/ThesisDoctoral Dissertation Electrical Engineering 201

High Speed Integrated Circuits for High Speed Coherent Optical Communications

With the development of (sub) THz transistor technologies, high speed integrated circuits up to sub-THz frequencies are now feasible. These high speed and wide bandwidth ICs can improve the performance of optical components, coherent optical fiber communication, and imaging systems. In current optical systems, electrical ICs are used primarily as driving amplifiers for optical modulators, and in receiver chains including TIAs, AGCs, LPFs, ADCs and DSPs. However, there are numerous potential applications in optics using high speed ICs, and different approaches may be required for more efficient, compact and flexible optical systems.This dissertation will discuss three different approaches for optical components and communication systems using high speed ICs: a homodyne optical phase locked loop (OPLL), a heterodyne OPLL, and a new WDM receiver architecture.The homodyne OPLL receiver is designed for short-link optical communication systems using coherent modulation for high spectral efficiency. The phase-locked coherent receiver can recover the transmitted data without requiring complex back-end digital signal processing to recover the phase of the received optical carrier. The main components of the homodyne OPLL are a photonic IC (PIC), an electrical IC (EIC), and a loop filter. One major challenge in OPLL development is loop bandwidth; this must be of order 1 GHz in order for the loop to adequately track and suppress the phase fluctuations of the locked laser, yet a 1 GHz loop bandwidth demands small (&lt;100 ps) propagation delays if the loop is to be stable. Monolithic integration of the high-speed loop components into one electrical and one photonic IC decreases the total loop delay. We have designed and demonstrated an OPLL with a compact size of 10 × 10 mm2, stably operating with a loop bandwidth of 1.1 GHz, a loop delay of 120 ps, a pull-in time of 0.55 μs and lock time of &lt;10 ns. The coherent receiver can receive 40 Gb/s BPSK data with a bit error rate (BER) of &lt;10-7, and operates up to 35 Gb/s with BER 10-12.The thesis also describes heterodyne OPLLs. These can be used to synthesize optical wavelengths of a broad bandwidth (optical wavelength synthesis) with narrow linewidth and with fast frequency switching. There are many applications of such narrow linewidth optical signal sources, including low phase noise mm-wave and THz-signal sources, wavelength-division-multiplexed optical transmitters, and coherent imaging and sensor systems. The heterodyne OPLL also has the same stability issues (loop delay and sensitivity) as the homodyne OPLL. In the EIC, a single sideband mixer operating using digital design principles (DSSBM) enables precisely controlled sweeping of the frequency of the locked laser, with control of the sign of the frequency offset. The loop's phase and frequency difference detector (PFD) uses digital design techniques to make the OPLL loop parameters only weakly sensitive to optical signal levels or optical or electrical component gains. The heterodyne OPLL operates stably with a loop bandwidth of 550 MHz and loop delay of &lt;200 ps. An initial OPLL design exhibited optical frequency (wavelength) synthesis from -6 GHz to -2 GHz and from 2 GHz to 9 GHz. An improved OPLL reached frequency tuning up to 25 GHz. The homodyne OPLL exhibits -110 dBc/Hz phase noise at 10 MHz offset and -80 dBc/Hz at 5 kHz offset.Finally, the thesis describes a new WDM receiver architecture using broadband electrical ICs. In the proposed WDM receiver, a set of received signals at different optical wavelengths are mixed against a single optical local oscillator. This mixing converts the WDM channels to electrical signals in the receiver photocurrent, with each WDM signal being converted to an RF sub-carrier of different frequency. An electrical IC then separately converts each sub-carrier signal to baseband using single-sideband mixers and quadrature local oscillators. The proposed receiver needs less complex hardware than the arrays of wavelength-sensitive receivers now used for WDM, and can readily adjust to changes in the WDM channel frequencies. The proposed WDM receiver concept was demonstrated through several system experiments. Image rejection of greater than 25 dB, adjacent channel suppression of greater than 20 dB, operation with gridless channels, and six-channel data reception at a total 15 Gb/s (2.5 Gb/s BPSK × 6-channels) were demonstrated

Novel Predistortion System for 4G/5G Small-Cell and Wideband Transmitters

To meet the growing demand for mobile data, various technologies are being introduced to wireless networks to increase system capacity. On one hand, large number of small-cell base stations are adopted to serve the reduced cell size; on the other hand, millimeter wave (mm-wave) systems with large antenna arrays that transmit ultra-wideband signals are expected in fifth generation (5G) networks. Power amplifiers (PAs), responsible for boosting the radio frequency (RF) signal power, are the most critical components in base station transmitters, and dominate the overall efficiency and linearity of the system. The design challenges to balance the contradictory requirements of efficiency and linearity of the PAs are usually addressed by linearization techniques, particularly the digital predistortion (DPD) system. However, existing DPD solutions face increasing difficulties keeping up with new developments in base station technologies. When considering sub-6 GHz small-cell base station transmitters, analog and RF predistortion techniques have recently received renewed attention due to their inherent low power nature. Their achievable linearization capacity is significantly limited, however, largely by their implementation complexity in realizing the needed predistortion models in analog circuitry. On the other hand, despite significant developments in DPD models for wideband signals, the implementations of such DPD models in practical hardware have received relatively little attention. Yet the conventional implementation of a DPD engine is limited by the maximum clock frequency of the digital circuitry employed and cannot be scaled to satisfy the growing bandwidth of transmitted signals for 5G networks. Furthermore, both analog and digital solutions require a transmitter-observation-receiver (TOR) to capture the PA outputs, necessitates the use of analog-to-digital converters (ADCs) whose complexity and power consumption increase with signal bandwidth. Such trend is not scalable for future base stations, and new innovations in feedback and training methods are required. This thesis presents a number of contributions to address the above identified challenges. To reduce the power overhead of the linearization system, a digitally-assisted analog-RF predistortion (DA-ARFPD) system that uses a novel predistortion model is introduced. The proposed finite-impulse-response assisted envelope memory polynomial (FIR-EMP) model allows for a reduction of hardware implementation complexity while maintaining good linearization capacity and low power overhead. A two-step small-signal-assisted parameter identification (SSAPI) algorithm is devised to estimate the parameters of the two main blocks of the FIR-EMP model, such that the training can be completed efficiently. A DA-ARFPD test bench has been built, which incorporates major RF components, to assess the validity of the proposed FIR-EMP scheme and the SSAPI algorithm. Measurement results show that the proposed FIR-EMP model with SSAPI algorithm can successfully linearize multiple PAs driven with various wideband and carrier-aggregated signals of up to 80~MHz modulation bandwidths for sub-6 GHz systems. Next, a hardware-efficient real-time DPD system with scalable linearization bandwidth for ultra-wideband 5G mm-wave transmitters is proposed. It uses a novel parallel-processing DPD engine architecture to process multiple samples per clock cycle, overcomes the linearization bandwidth limit imposed by the maximum clock rate of digital circuits used in conventional DPD implementation. Potentially unlimited linearization bandwidth could be achieved by using the proposed system with current digital circuit technologies. The linearization performance and bandwidth scalability of the proposed system is demonstrated experimentally using a silicon-based Doherty (DPA) with 400 MHz wideband signal operating at 28 GHz, and over-the-air measurements using a 64-element beamforming array with 800 MHz wideband signal, also at 28 GHz. The proposed DPD system achieves over 2.4 GHz linearization bandwidth using only a 300 MHz core clock for the digital circuits. Finally, to reduce the power consumption and cost of the TOR, a new approach to train the predistorter using under-sampled feedback signal is presented. Using aliased samples of the PA's output captured at either baseband or intermedia frequency (IF), the proposed algorithm is able to compute the coefficients of the predistortion engine to linearize the PA using a direct learning architecture. Experimentally, both the baseband and IF schemes achieve linearization performance comparable to a full-rate system. Implemented together with a parallel-processing based DPD engine on a field-programmable gate array (FPGA) based system-on-chip (SOC), the proposed feedback and training solution achieves over 2.4~GHz linearization bandwidth using an ADC operating at a clock rate of 200 MHz. Its performance is demonstrated experimentally by linearizing a silicon DPA with 200 MHz and 400 MHz signals in conductive measurements, and a 64-element beamforming array with 400 MHz and 800 MHz signals in over-the-air testing

Advanced Doherty power amplifier design for modern communication systems

Mobile communication technologies are becoming increasingly sophisticated and have experienced rapid evolution over the last few decades, and this is especially true for the base station transmitter. In response to the ever increasing demand in communication traffic and data throughput, largely driven by video based social media platforms, both spectral and power efficient device and systems are needed to fulfil the requirements. In terms of energy consumption, the power amplifier is an important component, and although developing efficient technologies for handset equipment is important, it is the base station element of the communications system that poses the greater challenge, having to deal with many channels simultaneously, resulting in the need to linearly and efficiently amplify highly dynamic phase and amplitude modulated signals possessing very large peak-to-average power ratios, at high power levels. This unique set of challenges has led to continuous research to improve the efficiency of amplifiers that can accommodate such signals, and the Doherty architecture has now become the architecture-of-choice. However, most of the previous research studies demonstrate Doherty performance enhancement through a ‘conventional’ design approach that uses one input source and a passive power splitter to deliver power to each half of the Doherty structure. They do not emphasize the additional efficiency and other performance improvements that are possible in Doherty amplifiers when using two different, independent and phase coherent input sources, attached to the input path of both main and auxiliary amplifiers. IV The novel research work presented in this thesis introduces an optimised design approach for Doherty amplifier architectures with individual input sources, as well as detailing a measurement architecture that is necessary to characterise such structures, using separate, phase-coherent input sources in a realistic measurement scenario. Finally, following extensive characterisation of a number of promising architectures, investigations around efficiency enhancement are focused around the adaption of gate bias applied to the auxiliary amplifier device, and identifying, for the first time, what is possible by generating different shaping functions that relate bias voltage to the magnitude of the input signal. One completely new area of research and novelty introduced in this work for example shows how choosing the right shaping function can give improved linearity and importantly linearisability by producing a flat gain over dynamic range. Note that linearisability is important, and is defined here as the term used to describe the ease with which the non-linearities of a device or power amplifier can be corrected. It is often assumed in power amplifier design that efficiency and power are the most important parameters, and that modern digital pre-distortion (DPD) techniques can easily correct any non-linearity that may result. Industry is now finding that this is not the case however, and the type and nature of the non-linearity in terms to AM-AM and AM-PM distortion is very important in determining of the degree of linearization possible

Linear Operation of Switch-Mode Outphasing Power Amplifiers

Radio transceivers are playing an increasingly important role in modern society. The ”connected” lifestyle has been enabled by modern wireless communications. The demand that has been placed on current wireless and cellular infrastructure requires increased spectral efficiency however this has come at the cost of power efficiency. This work investigates methods of improving wireless transceiver efficiency by enabling more efficient power amplifier architectures, specifically examining the role of switch-mode power amplifiers in macro cell scenarios. Our research focuses on the mechanisms within outphasing power amplifiers which prevent linear amplification. From the analysis it was clear that high power non-linear effects are correctable with currently available techniques however non-linear effects around the zero crossing point are not. As a result signal processing techniques for suppressing and avoiding non-linear operation in low power regions are explored. A novel method of digital pre-distortion is presented, and conventional techniques for linearisation are adapted for the particular needs of the outphasing power amplifier. More unconventional signal processing techniques are presented to aid linearisation of the outphasing power amplifier, both zero crossing and bandwidth expansion reduction methods are designed to avoid operation in nonlinear regions of the amplifiers. In combination with digital pre-distortion the techniques will improve linearisation efforts on outphasing systems with dynamic range and bandwidth constraints respectively. Our collaboration with NXP provided access to a digital outphasing power amplifier, enabling empirical analysis of non-linear behaviour and comparative analysis of behavioural modelling and linearisation efforts. The collaboration resulted in a bench mark for linear wideband operation of a digital outphasing power amplifier. The complimentary linearisation techniques, bandwidth expansion reduction and zero crossing reduction have been evaluated in both simulated and practical outphasing test benches. Initial results are promising and indicate that the benefits they provide are not limited to the outphasing amplifier architecture alone. Overall this thesis presents innovative analysis of the distortion mechanisms of the outphasing power amplifier, highlighting the sensitivity of the system to environmental effects. Practical and novel linearisation techniques are presented, with a focus on enabling wide band operation for modern communications standards

Solid-state technology for domestic microwave heating applications

The use of solid-state power for microwave heating, first proposed in the late 1960’s and early 1970’s, is now an area of growing interest and research for a number of stakekholders; semiconductor device manufacturers, domestic and commercial microwave oven manufacturers, large-scale heating industry and consumers. The traditional way of generating power for these applications has been through the use of a high power magnetron source, the power is then coupled into the cavity via a waveguide. Although cost effective, the magnetron source is limited in that it has a relatively small bandwidth (20MHz) which means that only a small number of modes are excited. The different ingredients in a meal often have different dielctric properties and require multi-mode excitations over the entire (2.4-2.5GHz) band to distribute heat evenly and prevent uneven heating of the load. Its other limitations include no direct means of quantifying forward and reflected powers, the transit time becoming an appreciable portion of the signal cycle which decreases efficiency has been well documented. The recent advances and developments in semiconductor device technology (LDMOS, HVLDMOS and GaN-on-Si) has alleviated some of the earlier obstacles relating to lowpower and poor-efficiency. However, concerns remain about cost, device reliability and output power levels. For example the relatively recent, sufficiently high power levels from a single transistor (300W, CW), and the use of new power combining techniques are factors that are increasing the viability of solid-state power in microwave heating. This thesis focuses on a proposed application that involves the use of RF generated power from a solid-state amplifier, at the heart of the SSPA is the “power transistor”, which generates power to heat the loads (e.g. food) in resonant cavities. From an energy consumption perspective, the solid-state source is a key element that must be designed to satisfy stringent efficiency requirements. Device and circuit related efficiencies are required to maintain an efficient transfer of power into the cavity under variable loading conditions which poses an even greater challenge. The delivery of power into a cavity iii under variable loading conditions usually leads to impedance mismatch, highly reflective states and associated heating inefficiency. Addressing this set of unique challenges has led to continuous research to improve the efficiency and reliability of power transistors. For example, new power transistor technologies (GaN, SiC) offer increased performance compared to traditional silicon components. These transistors can operate at higher power levels, frequencies and temperatures with an improved energy efficiency with respect to that guaranteed by previous generation. From a solid-state heating perspective most of this research has focused on high power and high efficiency PA architectures and device reliability, there is little literature addressing the importance of a coupling structures and the potential performance enhancements they may offer in solid-state implementations. The coupling structure plays an important role in transferring available SSPA power into the cavity to heat the load. The novel work presented in this thesis includes capturing cavity impedance behaviour of different cavity geometries under variable loading conditions and introduces a coupling architecture through which these changes are identified and optimally matched to maintain system and heating efficiency. Following extensive research into means of transferring SSPA power into the cavity efficiently, maintaining device reliability and realizing the goal of homogeneous heating, the study has led to the development of a novel coupling structure. This structure ensures an optimised match under variable loading conditions by incorporating harmonic tuning elements for improved efficiency. The novel research introduced in this work shows how device reliability and efficiency can be improved along with improving heating uniformity