Study and Design of 40 nW CMOS Temperature Sensor for Space Applications

In this paper, a novel CMOS temperature sensors based on sub-threshold MOS operation has been presented, which is designed for space and satellite applications. This proposed CMOS temperature sensor is enunciated good linearity between temperatures range from -55OC to 150OC with inaccuracy of 0.85 OC/V. This circuit is operated at supply 1V and static power consumption 40nW is achieved. The proposed circuit is based on the MOS threshold voltage and mobility. There are two type of sensor output in presented circuit first, voltage proportional to absolute temperature (PTAT) due to threshold voltage and second, negative temperature coefficient (NTC) due to mobility. This circuit is designed & simulated using Cadence analog & digital system design tools UMC90nm CMOS technology. The layout area of the circuit is 17.213μm  6.655μm. This is a low power and longer battery life for harsh environment, wireless sensor network applications etc.

An FPGA Noise Resistant Digital Temperature Sensor with Auto Calibration

In recent years, thermal sensing in digital devices has become increasingly important. From a security perspective, new thermal-based attacks have revealed vulnerabilities in digital devices. Traditional temperature sensors using analog-to-digital converters consume significant power and are not conducive to rapid development. As a result, there has been an escalating demand for low cost, low power digital temperature sensors that can be seamlessly integrated onto digital devices. This research seeks to create a modular Field Programmable Gate Array digital temperature sensor with auto one-point calibration to eliminate the excessive costs and time associated with calibrating existing digital temperature sensors. In addition, to support the auxiliary protection role, the sensor is evaluated alongside a RSA circuit implemented on the same chip, with methods developed to mitigate noise and power fluctuations introduced by the main circuit. The result is a digital temperature sensor resistant to noise and suitable for quick mass deployment in digital devices

Integrated temperature sensors in deep sub-micron CMOS technologies

textIntegrated temperature sensors play an important role in enhancing the performance of on-chip power and thermal management systems in today's highly-integrated system-on-chip (SoC) platforms, such as microprocessors. Accurate on-chip temperature measurement is essential to maximize the performance and reliability of these SoCs. However, due to non-uniform power consumption by different functional blocks, microprocessors have fairly large thermal gradient (and variation) across their chips. In the case of multi-core microprocessors for example, there are task-specific thermal gradients across different cores on the same die. As a result, multiple temperature sensors are needed to measure the temperature profile at all relevant coordinates of the chip. Subsequently, the results of the temperature measurements are used to take corrective measures to enhance the performance, or save the SoC from catastrophic over-heating situations which can cause permanent damage. Furthermore, in a large multi-core microprocessor, it is also imperative to continuously monitor potential hot-spots that are prone to thermal runaway. The locations of such hot spots depend on the operations and instruction the processor carries out at a given time. Due to practical limitations, it is an overkill to place a big size temperature sensor nearest to all possible hot spots. Thus, an ideal on-chip temperature sensor should have minimal area so that it can be placed non-invasively across the chip without drastically changing the chip floor plan. In addition, the power consumption of the sensors should be very low to reduce the power budget overhead of thermal monitoring system, and to minimize measurement inaccuracies due to self-heating. The objective of this research is to design an ultra-small size and ultra-low power temperature sensor such that it can be placed in the intimate proximity of all possible hot spots across the chip. The general idea is to use the leakage current of a reverse-bias p-n junction diode as an operand for temperature sensing. The tasks within this project are to examine the theoretical aspect of such sensors in both Silicon-On-Insulator (SOI), and bulk Complementary Metal-Oxide Semiconductor (CMOS) technologies, implement them in deep sub-micron technologies, and ultimately evaluate their performances, and compare them to existing solutions.Electrical and Computer Engineerin

Automatic Tuning of Digital Circuits.

Variation in transistors is increasing as process technology transistor dimensions shrink. Compounded with lowering supply voltage, this increased variation presents new challenges for the circuit designer. However, this variation also brings many new opportunities for the circuit designer to leverage as well. We present a time-to-digital converter embedded inside a 64-bit processor core, for direct monitoring of on-chip critical paths. This path monitoring allows the processor to monitor process variation and run-time variations. By adjusting to both static and dynamic operating conditions the impact of variations can be reduced. The time-to-digital converter achieves high-resolution measurement in the picosecond range, due to self-calibration via a self-feedback mode. This system is implemented in 45nm silicon and measured silicon results are shown. We also examine techniques for enhanced variation-tolerance in subthreshold digital circuits, applying these to a high fan-in, self-timed transition detection circuit that, due to its self-timing, is able to fully compensate for the large variation in subthreshold. In addition to mitigating variations we also leverage them for random number generation. We demonstrate that the randomness inherent in the oxide breakdown process can be extracted and applied for the specific applications of on-chip ID generation and on-chip true random number generation. By using dynamic automated self-calibrating algorithms that tune and control the on-chip circuitry, we are able to achieve extremely high-quality results. The two systems are implemented in 65 nm silicon. Measured results for the on-chip ID system, called OxID, show a high-degree of randomness and read-stability in the generated IDs, both primary prerequisites of a high-quality on-chip ID system. Measured results for the true random number generator, called OxiGen, show an exceptionally high degree of randomness, passing all fifteen NIST 800-22 tests for randomness with statistical significance and without the aid of a post-processor.Ph.D.Electrical EngineeringUniversity of Michigan, Horace H. Rackham School of Graduate Studieshttp://deepblue.lib.umich.edu/bitstream/2027.42/86390/1/rachliu_1.pd

Design methodology for thermal management using embedded thermoelectric devices

The main objectives of this dissertation is to investigate the prospects of embedded thermoelectric devices integrated in a chip package and to develop a design methodology aimed at taking advantage of the on-chip on-demand cooling capabilities of the thermoelectric devices. First a simulation framework is established and validated against experimental results, which helps to study the cooling capabilities of embedded thermoelectric coolers (TEC) in both a transient and steady state. The potential for up to 15°C of total cooling has been shown. The thermal simulation framework allows for rapid assessment of TEC and system level thermal performance. Next, the thesis develops a co-simulation environment that is capable of simulating the thermal and electrical domain and couples them to design intelligent TEC controllers. These controllers are implemented on chip and can leverage the transient cooling capability of the device. The controllers are simulated within the co-simulation environment and their potential to control high power chip events are thoroughly investigated. The system level overheads are considered and discussions on implementation techniques are presented. The co-simulation framework is also extended to allow for simulation of real predictive technology microprocessor cores and their workloads. Finally the thesis implements a fully on-chip autonomous energy system that takes advantage of the TEC in its reverse energy harvesting mode and uses the same device to harvest energy and use the energy to power the on-chip cooling circuit. This increases the overall energy efficiency of the cooler and verifies the TEC control methods.Ph.D

Analyses and design strategies for fundamental enabling building blocks: Dynamic comparators, voltage references and on-die temperature sensors

Dynamic comparators and voltage references are among the most widely used fundamental building blocks for various types of circuits and systems, such as data converters, PLLs, switching regulators, memories, and CPUs. As thermal constraints quickly emerged as a dominant performance limiter, on-die temperature sensors will be critical to the reliable operation of future integrated circuits. This dissertation investigates characteristics of these three enabling circuits and design strategies for improving their performances. One of the most critical specifications of a dynamic comparator is its input referred offset voltage, which is pivotal to achieving overall system performance requirements of many mixed-signal circuits and systems. Unlike offset voltages in other circuits such as amplifiers, the offset voltage in a dynamic comparator is extremely challenging to analyze and predict analytically due to its dependence on transient response and due to internal positive feedback and time-varying operating points in the comparator. In this work, a novel balanced method is proposed to facilitate the evaluation of time-varying operating points of transistors in a dynamic comparator. Two types of offsets are studied in the model: (1) static offset voltage caused by mismatches in mobilities, transistor sizes, and threshold voltages, and (2) dynamic offset voltage caused by mismatches in parasitic capacitors or loading capacitors. To validate the proposed method, dynamic comparators in two prevalent topologies are implemented in 0.25 μm and 40 nm CMOS technologies. Agreement between predicted results and simulated results verifies the effectiveness of the proposed method. The new method and the analytical models enable designers to identify the most dominant contributors to offset and to optimize the dynamic comparators\u27 performances. As an illustrating example, the Lewis-Gray dynamic comparator was analyzed using the balanced method and redesigned to minimize its offset voltage. Simulation results show that the offset voltage was easily reduced by 41% while maintaining the same silicon area. A bandgap voltage reference is one of the core functional blocks in both analog and digital systems. Despite the reported improvements in performance of voltage references, little attention has been focused on theoretical characterizations of non-ideal effects on the value of the output voltage, on the inflection point location and on the curvature of the reference voltage. In this work, a systematic approach is proposed to analytically determine the effects of two non-ideal elements: the temperature dependent gain-determining resistors and the amplifier offset voltage. The effectiveness of the analytical models is validated by comparing analytical results against Spectre simulation results. Research on on-die temperature sensor design has received rapidly increasing attention since component and power density induced thermal stress has become a critical factor in the reliable operation of integrated circuits. For effective power and thermal management of future multi-core systems, hundreds of sensors with sufficient accuracy, small area and low power are required on a single chip. This work introduces a new family of highly linear on chip temperature sensors. The proposed family of temperature sensors expresses CMOS threshold voltage as an output. The sensor output is independent of power supply voltage and independent of mobility values. It can achieve very high temperature linearity, with maximum nonlinearity around +/- 0.05oC over a temperature range of -20oC to 100oC. A sizing strategy based on combined analytical analysis and numerical optimization has been presented. Following this method, three circuits A, B and C have been designed in standard 0.18 ym CMOS technology, all achieving excellent linearity as demonstrated by Cadence Spectre simulations. Circuits B and C are the modified versions of circuit A, and have improved performance at the worst corner-low voltage supply and high threshold voltage corner. Finally, a direct temperature-to-digital converter architecture is proposed as a master-slave hybrid temperature-to-digital converter. It does not require any traditional constant reference voltage or reference current, it does not attempt to make any node voltage or branch current constant or precisely linear to temperature, yet it generates a digital output code that is very linear with temperature

Conception d'un capteur de température, d'un récepteur LVSD et d'un générateur de charge en technologie CMOS 0,18 um pour un scanner TEP/TDM

La recherche en imagerie moléculaire repose beaucoup sur les performances en tomographie d'émission par positrons (TEP). Les avancées technologiques en électronique ont permis d'améliorer la qualité de l'image fournie par les scanners TEP et d'en augmenter le champ d'application. Le scanner LabPET II, en développement à l'Université de Sherbrooke, permettra d'atteindre des résolutions spatiales inégalées.La conception de ce scanner requiert une très grande densité de détecteurs de l'ordre de 39 000 sur un anneau de 15 cm de diamètre par 12 cm de longueur axiale. D'autre part, l'Université de Sherbrooke mène également des travaux en tomodensitométrie (TDM) par comptage de photons individuels. Ces travaux s'insèrent dans un programme de recherche menant à réduire par un facteur 1,5 à 10 la dose de rayon X par rapport aux doses actuelles en TDM. Un circuit intégré (ASIC) a été développé pour supporter les performances attendues en TEP et en TDM. Cependant, la très grande densité de canaux rend inadéquate la vérification externe, sur circuits imprimés (PCB), des fonctionnalités des 64 canaux d'acquisition du circuit intégré actuellement en conception. Ainsi, un générateur de charge électronique a été conçu et intégré dans l'ASIC afin de pouvoir vérifier directement sur le circuit intégré ( On-Chip ) le fonctionnement de la chaine d'acquisition. Il permettra aussi de faire les tests pour le calcul de la résolution d'énergie et de la résolution en temps intrinsèque. La communication des données avec l'ASIC se fait par une ligne différentielle afin de maximiser l'immunité des signaux contre le bruit et d'assurer la vitesse de communication voulue.La norme Low-Voltage Differential Signaling (LVDS) a été choisie pour ce type de communication. En effet, trois récepteurs LVDS, basse consommation, ont été conçus et intégrés dans l'ASIC afin de recevoir les commandes de fonctionnement de l'ASIC à partir d'une matrice de portes programmables Field-Programmable Gate Array (FPGA) et de communiquer le signal d'horloge aux différents blocs. Pour augmenter la fiabilité du traitement effectué par l'électronique frontale, une mesure en température de l'ASIC est nécessaire. Un capteur de température basé sur la boucle à délais Delay-Locked Loop (DLL) a été conçu et intégré. En effet, la mesure de la température de l'ASIC permet d'intervenir en réalisant une compensation sur les mesures et en contrôlant le système de refroidissement en cas de sur-échauffement

Design of Digital SoC for Operation at High Temperatures

There is a growing demand for Systems-on-Chip, integrating microprocessors, on-chip memories, data converters and a variety of sensors, which are capable of reliable operation at high temperatures. For instance, modern aircraft industry demands microcontrollers and electric motors to operate at high temperatures, in order to replace present hydraulic structures. This thesis explains how to design digital SoC which are capable of reliable operation at high temperatures. The essential part of this thesis focuses on the design, implementation, fabrication and high-temperature measurements of on-chip Latch based SRAM, PowerPC e200 based microcontroller, digital temperature sensor and Flash A/D converter. Embedded on-chip SRAM modules are one of the most important components in the modern SoC. We analyze thermally-caused failures in the 6T SRAM cell and elaborate on its reliability. Further, we show that Latch based SRAM modules are preferable to 6T SRAM for reliable operation beyond 150C, by comparing two 1kB SRAM modules implemented in standard 0.18um SOI CMOS process. We demonstrate reliable SRAM operation at 275C (fmax = 10MHz, Ptot = 400mW), that is by far the highest reported operating temperature for digital on-chip SRAM module. Designing SoCs for reliable operation at elevated temperatures is a significant challenge, due to increased static leakage current, reduced carrier mobility, and increased electromigration. We propose to customize a PowerPC e200 based SoC by using a dynamically reconfigurable clock frequency, exhaustive clock gating, and electromigration-resistant power distribution network. We fabricated a 20x9mm2 chip implementing this design in 0.35um Bulk CMOS process. We present worldâs first PowerPC based SoC for reliable operation at 225C (fmax = 30MHz, Ptot = 1.2W). This design outperforms previously reported PowerPC based SoCs, which are not operational at temperatures beyond 125C. The on-chip measurements of the p-n junction temperature allow reliability improvements for the SoC that operates at high temperatures. Low-resolution temperature measurements are efficiently used for adjusting the optimal operation frequency and supply voltage. We used the Time-to-Digital conversion technique to design a fully-digital temperature sensor. We designed and simulated a fully-digital 5bit temperature sensor for 10C resolution temperature measurements in between Tj,min = -45C and Tj,max = 125C. Further, using a single clock cycle Time-to-Digital conversion technique, we present a fully-digital 5bit Pulse based Flash ADC implemented in 0.18um Bulk CMOS process. Measurement results demonstrate the state-of-the-art power efficiency result of 450 fJ/conv (fmax = 83MHz, Ptot = 900uW)