Design of reconfigurable multi-mode RF circuits

Wireless communication systems and devices have been developing at a much faster pace in the past few years. With the introduction of new applications and services and the increasing demand for higher data rate comes the need for new frequency bands and new standards. One critical issue for next generation wireless devices is how to support all of the existing and emerging bands while not increasing the cost and power consumption. A feasible solution is the concept of the software-defined radio where a single receiver can be reconfigured to operate in different modes, each of which supports one or several bands and/or standards. To implement such a reconfigurable receiver, reconfigurable RF building blocks, such as the LNA, mixer, VCO, etc., are required. This dissertation focuses on two key blocks: the low noise amplifier (LNA) and the voltage controlled oscillator (VCO). First the design, modeling and characterization of a multi-tap transformer are discussed. Simple mathematical calculations are utilized to estimate the inductances and coupling coefficients from the physical parameters of a multi-tap transformer. The design method is verified with several designed multi-tap transformers that are characterized up to 10 GHz using Momentum simulation results. The effect of switch loss on a switched multi-tap transformer is explored and a broadband lumped-element model of the multi-tap transformer is also proposed. Next a reconfigurable multimode LNA capable of single-band, concurrent dual-band, and ultra-wideband operation is presented. The multimode operation is realized by incorporating a switched multi-tap transformer into the input matching network of an inductively degenerated common source amplifier. The proposed LNA achieves single band matching at 2.8, 3.3, and 4.6 GHz; concurrent dual-band matching at 2.05 and 5.65 GHz; and ultra-wideband matching from 4.3 to 10.8 GHz. The chip was fabricated in a 0.13 m CMOS process, and occupies an area of 0.72 mm2, and has a power dissipation of 6.4 mW from a 1.2-V supply. Finally, a triple-mode VCO using a transformer-based 4th order tank with tunable transconductance cells coupling the primary and secondary inductor is introduced. The tank impedance can be re-shaped by the transconductance cells through the tuning of their biasing currents. With the control of biasing current, VCO is configured in three modes, capable of generating a single frequency in 3- and 5- GHz bands, respectively, and two frequencies in both 3- and 5- GHz bands simultaneously. The triple-mode VCO was fabricated in a 0.13 μm CMOS process, occupies an area of 0.16 mm2, and dissipates 5.6 mW from a 1.2-V supply

Advanced CMOS Integrated Circuit Design and Application

The recent development of various application systems and platforms, such as 5G, B5G, 6G, and IoT, is based on the advancement of CMOS integrated circuit (IC) technology that enables them to implement high-performance chipsets. In addition to development in the traditional fields of analog and digital integrated circuits, the development of CMOS IC design and application in high-power and high-frequency operations, which was previously thought to be possible only with compound semiconductor technology, is a core technology that drives rapid industrial development. This book aims to highlight advances in all aspects of CMOS integrated circuit design and applications without discriminating between different operating frequencies, output powers, and the analog/digital domains. Specific topics in the book include: Next-generation CMOS circuit design and application; CMOS RF/microwave/millimeter-wave/terahertz-wave integrated circuits and systems; CMOS integrated circuits specially used for wireless or wired systems and applications such as converters, sensors, interfaces, frequency synthesizers/generators/rectifiers, and so on; Algorithm and signal-processing methods to improve the performance of CMOS circuits and systems

Low power digitally controlled oscillator for IoT applications

This work is focused on the design of a Low Power CMOS DCO for IEEE 802.11ah in IoT applications. The design methodology is based on the Unified current-control model (UICM), which is a physics-based model and enables an accurate all-region model of the operation of the device. Additionally, a transformer-based resonator has been used to solve the low-quality factor issue of integrated inductors. Two digitally controlled oscillators (DCO) have been implemented to show the advantages of utilizing a transformedbased resonator and the methodology based on the UICM model. These designs aim for the operation in low voltage supply (VDD) since VDD scaling is a trend in systems-onchip (SoCs), in which the circuitry is mostly digital. Despite the degradation caused by VDD scaling, new RF and analog circuits must deliver similar performance of the older CMOS nodes. The first DCO design was a low power LC-tank DCO, implemented in 40nm bulk-CMOS. The first design presented a DCO operating at 45% of the nominal VDD without compromise the performance. By reducing the VDD below the nominal value, this DCO reduces power consumption, which is a crucial feature for IoT circuits. The main contribution of this first DCO is the reduction of VDD scaling impact on the phase-noise do the DCO. The LC-based DCO operates from 1.8 to 1.86 GHz. At the maximum frequency and 0.395V VDD, the power consumption is a mere 380 W with a phase-noise of -119.3 dBc/Hz at 1 MHz. The circuit occupies an area of 0.46mm2 in 40 nm CMOS, mostly due to the inductor. The second DCO design was a low-power transformer-based DCO design, implemented in 28nm bulk-CMOS. This second design aims for the VDD reduction to below 0.3 V. Operating in a frequency range similar to the LC-based DCO, the transformer-based DCO operated with 0.280V VDD with a power consumption of 97 W. Meanwhile, the phase-noise was -101.95 dBc/Hz at 1 MHz. Even in the worst-case scenario (i.e., slow-slow and 85oC), this second DCO was able to operate at 0.330V VDD, consuming 126 W, while it keeps a similar phase-noise performance of the typical case. The core circuit occupies an area of 0.364 mm2.Este trabalho objetiva o projeto de um DCO de baixa potência em CMOS para aplicações de IoT e aderentes ao padrão IEEE 802.11ah. A metodologia de projeto é baseada no modelo de controle de corrente unificado (UICM), que é um modelo com embasamento físico que permite uma operação precisa em todas as regiões de operação do dispositivo. Adicionalmente, é utilizado um ressonador baseado em transformador visando solucionar os problemas provenientes do baixo fator de qualidade de indutores integrados. Para destacar as melhorias obtidas com o projeto do ressonador baseado em transformador e com a metodologia baseada no modelo UICM, dois projetos de DCO são realizados. Esses projetos visam a operação com baixa tensão de alimentação (VDD), uma vez que o escalonamento do VDD é uma tendência em sistemas em chip (SoCs), em que o circuito é majoritariamente digital. Independente da degradação causada pelo escalonamento de VDD, circuitos analógicos e de RF atuais devem oferecer desempenho semelhante ao alcançado em tecnologias CMOS mais antigas. O primeiro projeto foi um DCO de baixa potência com tanque LC, implementado em tecnologia bulk-CMOS de 40nm. O primeiro projeto apresentou uma operação a 45% do VDD nominal sem comprometer o desempenho. Ao reduzir o VDD abaixo do valor nominal, este DCO reduz o consumo de energia, que é uma característica crucial para circuitos IoT. A principal contribuição deste DCO é a redução do impacto do escalonamento do VDD no ruído de fase. O DCO com tanque LC opera de 1,8 a 1,86 GHz. Na frequência máxima e com VDD de apenas 0,395V, o consumo de energia é 380 W e o ruído de fase é -119,3 dBc/Hz a 1 MHz. O circuito ocupa uma área de 0.46mm2 em processo CMOS de 40 nm. O segundo projeto foi um DCO de baixa potência baseado em transformador, implementado em tecnologia bulk- CMOS de 28nm. Este projeto visa a redução de VDD abaixo de 0,3 V. Operando em uma faixa de frequência semelhante ao primeiro DCO, o DCO baseado em transformador opera com VDD de 0,280V e com consumo de potência de 97 W. O ruído de fase foi de -101,95 dBc/Hz a 1 MHz. Mesmo no pior caso de processo, este DCO opera a um VDD de 0,330V, consumindo 126 W, com o ruído de fase semelhante ao caso típico. O circuito ocupa uma área de 0.364mm2

Quadrature LC VCO with passive coupling and phase combining network

A circuit and method for generating a signal is disclosed. The circuit includes a set of wide tuning LC tanks, a set of core transistors cross coupled to the set of wide tuning LC tanks, and a combining network coupled to the set of wide tuning LC tanks and the set of core transistors. The combining network further includes a set of inputs connected to the set of wide tuning LC tanks and the set of core transistors, a set of coupling transistors connected to the set of inputs, a set of source inductors connected to the set of coupling transistors, a coupling capacitor connected to the set of source inductors, a load resistor connected to the coupling capacitor. The combining network combines the set of inputs and the signal is delivered to the load resistor as a fourth order harmonic.Board of Regents, University of Texas Syste

Energy-Efficient Wireless Circuits and Systems for Internet of Things

As the demand of ultra-low power (ULP) systems for internet of thing (IoT) applications has been increasing, large efforts on evolving a new computing class is actively ongoing. The evolution of the new computing class, however, faced challenges due to hard constraints on the RF systems. Significant efforts on reducing power of power-hungry wireless radios have been done. The ULP radios, however, are mostly not standard compliant which poses a challenge to wide spread adoption. Being compliant with the WiFi network protocol can maximize an ULP radio’s potential of utilization, however, this standard demands excessive power consumption of over 10mW, that is hardly compatible with in ULP systems even with heavy duty-cycling. Also, lots of efforts to minimize off-chip components in ULP IoT device have been done, however, still not enough for practical usage without a clean external reference, therefore, this limits scaling on cost and form-factor of the new computer class of IoT applications. This research is motivated by those challenges on the RF systems, and each work focuses on radio designs for IoT applications in various aspects. First, the research covers several endeavors for relieving energy constraints on RF systems by utilizing existing network protocols that eventually meets both low-active power, and widespread adoption. This includes novel approaches on 802.11 communication with articulate iterations on low-power RF systems. The research presents three prototypes as power-efficient WiFi wake-up receivers, which bridges the gap between industry standard radios and ULP IoT radios. The proposed WiFi wake-up receivers operate with low power consumption and remain compatible with the WiFi protocol by using back-channel communication. Back-channel communication embeds a signal into a WiFi compliant transmission changing the firmware in the access point, or more specifically just the data in the payload of the WiFi packet. With a specific sequence of data in the packet, the transmitter can output a signal that mimics a modulation that is more conducive for ULP receivers, such as OOK and FSK. In this work, low power mixer-first receivers, and the first fully integrated ultra-low voltage receiver are presented, that are compatible with WiFi through back-channel communication. Another main contribution of this work is in relieving the integration challenge of IoT devices by removing the need for external, or off-chip crystals and antennas. This enables a small form-factor on the order of mm3-scale, useful for medical research and ubiquitous sensing applications. A crystal-less small form factor fully integrated 60GHz transceiver with on-chip 12-channel frequency reference, and good peak gain dual-mode on-chip antenna is presented.PHDElectrical and Computer EngineeringUniversity of Michigan, Horace H. Rackham School of Graduate Studieshttp://deepblue.lib.umich.edu/bitstream/2027.42/162975/1/jaeim_1.pd

A Low Phase Noise Wide-Tuning Range Class-F VCO Based on a Dual-Mode Resonator in 65nm CMOS

A Voltage Controlled Oscillator (VCO) is a critical building block in the design of current frequency synthesizers for RF system applications. State-of-the-art operation defines that an oscillator should have the best spectral purity while consuming low amount of power for a wide tuning range. With this in mind, this work presents a low phase noise wide tuning range ClassF VCO using a dual-mode resonator. In comparison to other conventional wideband oscillators, the proposed capacitively/inductively-coupled resonator will integrate the benefits of Class-F voltage control oscillators and dual-mode switching networks to obtain simultaneous low phase noise and wide-tuning range. The proposed structure, prototyped in 65nm TSMC CMOS technology, shows a 2.14 – 4.22GHz continuous tuning range, phase noise figure-of-merit (FoM) of 192.7dB at 2.3GHz and better than 188dB across the entire operating frequency range. The oscillator consumes 15-16.4mW from a 0.6V supply and occupies an active area of 0.7mm^2 . In conclusion, the proposed resonator achieves 2- 3dB phase noise improvement while achieving 65% overall tuning range when compared to a typical class-F VCO architecture

Innovative Design and Realization of Microwave and Millimeter-Wave Integrated circuits

Ph.DDOCTOR OF PHILOSOPH

SiGe-based broadband and high suppression frequency doubler ICs for wireless communications

制度:新 ; 報告番号:甲3419号 ; 学位の種類:博士(工学) ; 授与年月日:2011/9/15 ; 早大学位記番号:新574

Integrated radio frequency synthetizers for wireless applications

This thesis consists of six publications and an overview of the research topic, which is also a summary of the work. The research described in this thesis concentrates on the design of phase-locked loop radio frequency synthesizers for wireless applications. In particular, the focus is on the implementation of the prescaler, the phase detector, and the chargepump. This work reviews the requirements set for the frequency synthesizer by the wireless standards, and how these requirements are derived from the system specifications. These requirements apply to both integer-N and fractional-N synthesizers. The work also introduces the special considerations related to the design of fractional-N phase-locked loops. Finally, implementation alternatives for the different building blocks of the synthesizer are reviewed. The presented work introduces new topologies for the phase detector and the chargepump, and improved topologies for high speed CMOS prescalers. The experimental results show that the presented topologies can be successfully used in both integer-N and fractional-N synthesizers with state-of-the-art performance. The last part of this work discusses the additional considerations that surface when the synthesizer is integrated into a larger system chip. It is shown experimentally that the synthesizer can be successfully integrated into a complex transceiver IC without sacrificing the performance of the synthesizer or the transceiver.reviewe